HOME: Verilog

What is Verilog?

Verilog describes the functionality of hardware designs. A synthesis tool converts these descriptions into an actual design containing combinational and sequential elements (gates, flip-flops, and wires).

Verilog vs. VHDL

Verilog

Simpler syntax based on the C language. Generally preferred for its brevity and ease of learning for software programmers.

VHDL

Based on Ada and Pascal. It is strongly typed and more verbose, often used in government and aerospace legacy projects.

Abstraction Levels

Verilog defines four abstraction levels to implement modules. To the external environment, a module looks the same regardless of how it is implemented internally.

1. Behavioral Level

The highest level of abstraction. Implementation resembles C programming. It focuses on the algorithm without worrying about specific hardware details.

2. Dataflow Level

Specifies how data flows and processes through the circuit. Often uses assign statements and equations to describe signals.

3. Gate Level

Describes the design using logic gates (AND, OR, NOT) and the interconnections between them. Similar to a netlist.

4. Switch Level

The lowest level of abstraction. Implements design in terms of switches (transistors) and storage nodes. Rarely used in modern high-level design.

Understanding RTL

RTL (Register Transfer Level) is a term you will hear constantly in digital design. It refers to a combination of Dataflow and Behavioral modeling.

A design is typically implemented using a mix of these styles to achieve the most efficient simulation and synthesis results.

What You Will Learn

Category	Key Topics
Basics	Lexical Conventions, Data Types, Modules, Ports
Control Flow	Operators, If/Else, Case Statements, Loops, Blocking vs Non-Blocking
Verification	Writing Testbenches, System Tasks, Procedural Timing
Advanced	User-defined Primitives, Scheduling Semantics, Generate Blocks, FSM

Introduction to Verilog HDL