Flip-Flops Quiz | VLSI Trainers Flip-Flops Quiz 1. A flip-flop differs from a latch because: a) A flip-flop is edge-triggered, whereas a latch is level-sensitive b) A flip-flop can store more bits c) A latch uses fewer transistors d) A flip-flop is asynchronous always Next 2. In a master-slave D flip-flop, when the clock is high, which stage is active? a) Master stage b) Slave stage c) Both master and slave d) None Next 3. If in a JK flip-flop, J = K = 1, what is the behavior? a) Set b) Reset c) Toggle d) No change Next 22. What is the hold time requirement of a flip-flop? a) Input must remain stable for some time before clock edge b) Input must remain stable for some time after clock edge c) Output must be stable during clock high d) Output must toggle immediately Submit Quiz
