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When data is transferred across a PCIe (Peripheral Component Interconnect Express) interface, it is not always a full 32-bit or 64-bit word. To specify which bytes within a data word are valid or should be written/read, the Byte Enable fields are used. Let’s go step by step through the rules governing byte enables and understand […]
Chapter 5.4(a) – Understanding Byte Enable Rules in PCIe Transactions Read More »
1. Motivation PCI Express (PCIe) replaces the shared-bus model of PCI with a serial, packet-based interconnect.Rather than using parallel control and data lines, PCIe organizes every transaction—memory reads/writes, configuration accesses, I/O operations, and messages—into packets that move through a layered architecture. This design improves: 2. How the Packet-Based Approach Works Each PCIe transaction begins in
Chapter 5.1 – Introduction to Packet-Based Protocol in PCI Express Read More »
Introduction to Assertions Assertions are statements used to validate the behavior of a design during simulation.They help catch protocol violations, timing errors, and unexpected signal interactions early in the verification cycle. In simple terms — “Assertions are design checkers that continuously monitor whether design behavior meets the expected protocol.” Why Assertions Are Important Assertions improve:
SystemVerilog Assertions (SVA) — Complete Beginner Guide Read More »
SystemVerilog packages are powerful containers for reusable code such as data types, parameters, functions, classes, and tasks. They help engineers write modular and consistent designs by preventing type mismatches and enabling code sharing across modules, interfaces, and testbenches. In this post, we’ll explore package syntax, importing methods, common pitfalls, and examples that every VLSI learner
Packages in System Verilog Read More »
Learn about SystemVerilog data types including integer, logic, real, nets, enums, strings, and more with examples and code snippets. 🔹 Introduction SystemVerilog provides a rich set of data types that help in modeling both hardware and testbenches efficiently. Unlike older Verilog, it introduces strong typing, signed/unsigned control, and advanced user-defined types. 🔹 Integer Data Types
SystemVerilog Data Types Read More »
“Learn System Verilog unions – packed, unpacked, and tagged. Understand syntax, usage, and examples with simulation results for RTL and verification.”
System Verilog Union – Packed, Unpacked, and Tagged Read More »
Data-flow modeling is a higher level of abstraction in Verilog compared to gate-level modeling. It focuses on how data moves through a design, rather than describing individual gates. This makes the design more compact, easier to write/modify, and closer to RTL style while still retaining some explicitness in signal behavior. Why Use Data-Flow Modeling As
Data-Flow Modeling in Verilog: Concepts, Rules & Uses Read More »
Introduction: Advanced Peripheral Bus (APB) is the part of Advanced Microcontroller Bus Architecture (AMBA) family protocols. The Latest version of APB is v2.0, which was a part of AMBA 4 release. It is a low-cost interface and it is optimized for minimal power consumption and reduced interface complexity. Unlike AHB, it is a Non-pipelined protocol,
Hi, Myself Chethan D C . I have 3.5 years of experience in VLSI industry. working as design verification engineer from 2021
My Journey in VLSI Industry Read More »
