INTRODUCTION TO VERILOG

History : Lorem ipsum dolor sit amet, consectetur adipiscing elit. Ut elit tellus, luctus nec ullamcorper mattis, pulvinar dapibus leo. Beginning              Verilog was one of the first modern hardware description languages to be invented. It was created by Prabhu Goel and Phil Moorby during the winter of 1983/1984. The […]

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K – Map

2.5 KARNAUGH MAP (K-MAP) A Boolean expression may have many different forms. WiththeuseofK-map,thecomplexityofreducingexpressionbecomeseasyandBooleanexpressionobtained is simplified. K-map also be said as pictorial form of truth table. K-map is alternative way of simplifying logic circuits. Instead of using Boolean algebra simplification techniques, you can transfer logic values from aBoolean statement or a truth table into a Karnaugh

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Digital Electronics

Chapter 1 : 1.1 Introduction Electronic systems usually deal with information. Representation of information is called a signal. Signal in electronics is generally in form of voltage or current. Value of a signal is proportional to some physical quantity and it gives information about it. For example, temperature represented in terms of voltage signal. There

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Introduction to IC Technology

IC TECHNOLOGY in VLSI           The invention of vacuum tubes and associated electronic circuits has led to the endless development of electronics, which is known as vacuum tube electronics. Afterward the evolution of solid state devices and consequent development of integrated circuits are responsible for the present status of communication, computing

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System Verilog Interview Questions and Answers

1] What is the Difference between Param and typedef in System Verilog ? In SystemVerilog, both param and typedef are used to define constants or custom data types, but they serve different purposes. Here is the difference between param and typedef in SystemVerilog: param: typedef: 2] What is `timescale in System Verilog? In SystemVerilog, the `timescale directive is used to specify the time

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What are some common scenarios in System Verilog where race conditions can occur?

In SystemVerilog, race conditions can occur in various scenarios where multiple processes or threads access and modify shared variables simultaneously. Here are some common scenarios where race conditions can occur: It is important to note that these are just a few examples of common scenarios where race conditions can occur in System Verilog. It is

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X-Propagation in VLSI

X-propagation in VLSI refers to the propagation of the ‘X’ value, which represents an unknown logic value, through different logic gates in a VLSI (Very Large Scale Integration) circuit. When a simulator is unable to determine whether a logic value should be a ‘0’ or a ‘1’, it assigns an ‘X’ value. This can lead

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