UNIT-V Sequential Circuit Description Component test and Verification

SEQUENTIAL MODELS In digital circuits, storage of data is done either by feedback, or by gate capacitances that are refreshed frequently. Pending : Fig.181 Sequential models FEEDBACK MODEL: Pending : Fig.182 Feedback Mode CAPACITIVE MODEL Pending : Fig.183Capacitive model When c becomes 1 the value of D is saved in the input gate of the

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UNIT-IV SWITCH LEVEL MODELLINGSYSTEM TASKS, FUNCTIONS, AND COMPILER DIRECTIVES

In today’s environment the MOS transistor is the basic element around which a VLSI is built. Designers familiar with logic gates and their configurations at the circuit level may choose to do their designs using MOS transistors. Verilog has the provision to do the design description at the switch level using such MOS transistors. Switch

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MODULE

MODULE        Any Verilog program begins with a keyword – called a “module.” A module is the name given to any system considering it as a black box with input and output terminals as shown in Fig.5. The terminals of the module are referred to as ‘ports’. The ports attached to a module

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