Introduction:
Advanced Peripheral Bus (APB) is the part of Advanced Microcontroller Bus Architecture (AMBA) family protocols. The Latest version of APB is v2.0, which was a part of AMBA 4 release. It is a low-cost interface and it is optimized for minimal power consumption and reduced interface complexity. Unlike AHB, it is a Non-pipelined protocol, used to connect low-bandwidth peripherals. Mostly, used to connect the external peripheral to the SOC.
In APB, every transfer takes a least two clock cycles (SETUP Cycle and ACCESS cycle) to complete. It can also interface with AHB and AXI protocols using the bridges in between.
The above diagram depicts a block diagram of a system. The High-performance ARM processor is the Core of the System. The other components like High-bandwidth on-chip RAM, DMA bus master and High-bandwidth Memory Interface are connected to the Core by system bus, which is AHB in this case. The other low bandwidth peripherals like UART, Timer, Keypad and PIO are connected to the system bus through the Bridge by using peripheral bus, here it is APB bus. In this scenario, the Bridge acts as the AHB slave corresponding to the Core Master and it also acts as the APB Master corresponding to remaining low-bandwidth external peripherals.
Generally there won’t be any component that produces the APB transfers. The AHB to APB Bridge is the only component that acts as the APB master in a system.
- From the block diagram shown above,