Digital Electronics – unit II

• (Pending – Pre MCQ)

THEORY:
Binary Adder and Subtractor
The operation of adding two binary numbers is one of the fundamental tasks performed by a digital
computer. The four basic addition operations are 0 + 0 = 0, 1 + 0 = 1, 0 + 1 = 1 and 1 + 1 = 10. In the
first three operations, each binary addition gives sum as one bit, i.e., either 0 or 1.

But the fourth addition operation gives a sum that consists of two binary digits. In such result of the
addition, lower significant bit is called as the sum bit, whereas the higher significant bit is called as the carry bit. The logic circuits which are designed to perform the addition of two binary numbers are
called as binary adder circuits. In this article we are going to look at the binary addition performed by
various adder circuits.

Half Adder

A logic circuit block used for adding two one bit numbers or simply two bits is called as a half adder
circuit. This circuit has two inputs which accept the two bits and two outputs, with one producing sum output and other produce carry output.

As we discussed above that binary addition is commonly performed by Ex-OR gate, but for the first
three rules, it performs the binary addition and when the two inputs are logic 1, it does not develop any carry.

To accomplish the binary addition with Ex-OR gate, there is need of additional circuitry to perform the
carry operation. Hence, a half adder is formed by connecting AND gate to the input terminals of the
Ex-OR gate so as to produce the carry as shown in below figure. 

(Pending- diagram)

In the above half adder, inputs are labeled as A and B. The sum output is labeled with the summation
symbol? and the carry output or carry out is labeled with Co. Half adder is mainly used for addition of
augend and addend of first order binary numbers. 

Half adder has limited number of applications, and practically not used in the application especially
multi-digit addition. In such applications carry of the previous digit addition must be added along with
two bits; hence it is three bits addition. 

Full Adder 

A binary full adder is a multiple output combinational logic network that performs the arithmetic sum
of three input bits. As we have seen that the half adder cannot respond to the three inputs and hence the
full adder is used to add three digits at a time.

It consists of three inputs, in which two are input variables represent the two significant bits to be
added, labeled as A and B, whereas the third input terminal is the carry from the previous lower
significant position and labeled as Cin. The two outputs are  sum and a carry outputs which are  labeled as ? and Cout respectively. 

(Pending – diagram)

Full adder can be formed by combining two half adders and an OR gate as shown in above where
output and carry-in of the first adder becomes the input to the second half adder that produce the total sum output. The total carry out is produced by ORing the two half adder carry outs as shown in figure. The full adder block diagram and truth table is shown below. 

(Pending – diagram and table)

Binary Subtraction Circuits

Subtraction is a mathematical operation in which one integer number is deducted from another to
obtain the equivalent quantity. The number from which other number is to be deducted is called as
minuend and the number subtracted from the minuend is called subtrahend. Similar to the binary
addition, binary subtraction is also has four possible alternative operations.

The above figure shows the four possible rules or elementary operations of the binary subtractions. In all the operations, each subtrahend bit is deducted from the minuend bit.

But in the second rule, minuend bit is smaller than the subtrahend bit, hence 1 is borrowed to perform
the subtraction. Similar to the adder circuits, subtraction circuits are also classified as half subtractors, full subtractors and parallel subtractors.

Half Subtractors

A half subtractor is a multiple output combinational logic network that does the subtraction of two bits of binary data. It has input variables and two output variables. Two inputs are corresponding to two input bits and two output variables corresponds to the difference bit and borrow bit.

The binary subtraction is also performed by the Ex-OR gate with additional circuitry to perform the
borrow operation. Thus, a half subtractor is designed by an Ex-OR gate including AND gate with A
input complemented before fed to the gate.

The block model, truth table and logic diagram of a half subtractor shown in above figure. This circuit
is similar to the half adder with only difference in input A i.e., minuend which is complemented before
applied at the AND gate to implement the borrow output.

In case of multi-digit subtraction, subtraction between the two digits must be performed along with
borrow of the previous digit subtraction, and hence a subtractor needs to have three inputs. Therefore, a half subtractor has limited applications and strictly it is not used in practice.

Full Subtractor

A combinational logic circuit performs a subtraction between the two binary bits by considering
borrow of the lower significant stage is called as the full subtractor. In this, subtraction of the two
digits is performed by taking into consideration whether a 1 has already borrowed by the previous
adjacent lower minuend bit or not.

It has three input terminals in which two terminals corresponds to the two bits to be subtracted
(minuend A and subtrahend B), and a borrow bit Bi corresponds to the borrow operation. There are
two outputs, one corresponds to the difference D output and other borrow output Bo as shown in figure along with truth table.

By deriving the Boolean expression for the full subtractor from above truth table, we get the
expression that tells that a full subtractor can be implemented with half subtractors with OR
shown in figure below.

By comparing the adder and subtractor circuits or truth tables, one can observe that the output D in the full subtractor is exactly same as the output S of the full adder. And the only difference is that input variable A is complemented in the full subtractor.

Therefore, it is possible to convert the full adder circuit into full subtractor by simply complementing
the input A before it is applied to the gates to produce the final borrow bit output Bo.

Parallel Binary Adders

As we discussed that a single full adder performs the addition of two one bit numbers and an input
carry. For performing the addition of binary numbers with more than one bit, more than one full adder
is required depends on the number bits. Thus, a parallel adder is used for adding all bits of the two
numbers simultaneously.

By connecting a number of full adders in parallel, n-bit parallel adder is constructed. From the below
figure, it is to be noted that there is no carry at the least significant position, hence we can use either a half adder or made the carry input of full adder to zero at this position.

The figure below shows a parallel 4 bit binary adder which has three full adders and one half-adder.
The two binary numbers to be added are A3A2A1A0 and B3B2B1B0 which are applied to the
corresponding inputs of full adders. This parallel adder produces their sum as C4S3S2S1S0 where C4
is the final carry.

In the 4 bit adder, first block is a half and a carry bit C1. Next block should be full adder as there are three inputs applied to it. Hence this full adder produces their sum S1 and a carry C2. This will be followed by other two full adders and thus the final sum is C4S3S2S1S0.

Most commonly Full adders designed in dual in a 4 bit full adder. Arithmetic and Logic Unit of a unit computer consist of these parallel adders to perform the addition of binary numbers.

MULTIPLEXER:

• Multiplexer is a special type of combinational circuit.
• The figure below shows the n x 1 multiplexer and its equivalent circuit representation.
• There are ‘n’ data inputs, 1 output and ‘m’ select lines, i.e.2
• A multiplexer is a digital circuit which selects one of the n output. The selection of one of the n inputs is done by the select inputs
• To select ‘n’ inputs, ‘m’ select lines such that2
• Depending on the digital code applied at the select inputs, one out of ‘n’ data sources is elected and transmitted to the single output.
• As shown in the figure, the multiplexer acts like a digitally controlled single pole, multiple way switch. 
• The output gets connected to only one of the ‘n’ data inputs at given instant of time. 
• It is also called DATASELECTOR. 
• Different types of multiplexers are available viz. 2 to 1, 4 to 1, 8 to 1, 16 to 1 and on wards.
• Multiplexers are needed in most of electronics systems, where the digital data is available on more than one lines, and it becomes necessary to route this data over a single line. 
• Many logical functions can be implemented using Multiplexer. 

2 X 1Multiplexer  

(Pending –  diagram)

It has two data inputs I0 and I1, one select input S, and one output Y. 

(Pending – table)

Boolean Equation : Y = S’I0 + SI1

(Pending – diagram)

Working: 

• When S=0, the upper AND gate will turn ON and lower AND gate will turn OFF, and so the input 0 appears in the output. 
• When S=1, the upper AND gate will turn OFF and lower AND gate will turn ON, inputI1 appears in the output. 

4 X 1Multiplexer 

• It has four data inputs I3, I2 
• Here 2n=4 inputs, i.e. n=2 select lines and m = 1output 

(Pending – diagram)

Truth Table (Pending – truth table) 

Working 

• According to the truth table, when S1 S0=00, the input I0 is selected and routed to the output
• When S1 S0=01, the input I1 is selected and routed to the output.
•  Similarly, when S1 S0=10, then Y=I2 & when S1 S0=11, then Y=I3.  
• Boolean Equation
  Y = S1’S0’I0 + S1’S0I1 + S1S0’I2 + S1S0I3

(Pending – diagram)

Circuit Diagram

(Pending – circuit diagram)

DEMULTIPLEXER:

(Pending – diagram)
Fig.: Illustration of demultiplexer

• It has one input common data, ‘n’ select lines and ‘m’ output lines.
• A demultiplexer performs the reverse operation of a multiplexer i.e. it receives one input and distributes it over several outputs.
• At a time only one output line is selected by the select the selected output line.
• Relation between ‘n’ output lines and m select lines is as follows: n = 2m

1 X 4Demultiplexer 

• 1 to 4 Demultiplexer has one data input F; select line inputs a,b and four outputs A, B, C & 
• The select lines control the data to be routed. It helps in selecting the output on which the data will be routed

Switch Representation 

• Based on the switch control, the input is routed to particular output 

(Pending – diagram)

Switching representation of 1 X 4 Table 3.4: Truth table of 1 X 4 demultiplexer 

Boolean Equation;                                                                                                                             A= Fb′a′;      B = Fb′a;    C= Fba 

Working 

• When ab=”00”, the input data F is routed to the output A 
• When ab=”01”, the input data F is routed to the output B 
• When ab=”10”, the input data F is routed to the output C 
• When ab=”11”, the input data F is routed to the output D

 (Pending – diagram)

Circuit diagram :

(Pending – diagram)

ENCODER 

• It is a combinational circuit. 
• It has ‘n’ input lines & ‘m’ output lines. 
• An encoder produces an ‘m’ bit binary code corresponding to the digital input number of ‘n’ bits.
• Many types of Encoders – Octal to Binary(8 to 3), Decimal to BCD(10 to 4) etc
• The block diagram is as shown below, Priority Encoder 
• This is special type of encoder. 
• Priorities are given to the input lines.
• If two or more input lines are ‘1’ at the same time, then the input line with highest priority will be considered. 
• The block diagram is shown below.
• The truth table of priority encoder is as given below
• There are four inputs, D0 through D3 and outputs Y1 and Y0. Out of the four inputs D3 has the highest priority and D0 has the lowest priority. 
• That means if D3 = 1 then Y1Y0 = 11 irrespective of the other inputs. Similarly if D3 = 0 and D2 = 1 then Y1Y0 = 10 irrespective of other input.
  

Truth table – 

(Pending – table and k map)

Below figures shows the circuit diagram of Priority Encoder.

(Pending – diagram) 

Octal to Binary (8 to 3)Encoder

Table : Truth table of octal to binary encoder

(Pending – table) 

• It has 8 input lines & 3 output lines. 
• Corresponding to the eight input octal numbers we get three bit binary output.
• In encoders only one input will have a one value at any given time

Circuit diagram 

(Pending – circuit diagram)

DECODER

(Pending – diagram)

• Decoder is a device which does the reverse operation of Encoder. It is a combinational circuit that converts binary information from ‘n’ input lines to a maximum of ‘2n’ unique output lines.
• Decoder is identical to a demultiplexer without any data input. 
• E.g.: 2 to 4 Decoder, 3 to 8 Decoder, BCD to Seven Segment Decoder

• I0 & I1 are two inputs whereas y3, y2, y1 & y0 are four outputs.
• The truth table shows that each output is ‘1’ for only a specific combination of inputs. 

(Pending – diagram)

Boolen Equation 

      y0 = I̅1I̅0           y1= I̅1I0;                                    y2 = I1I̅0;          y3 =I1I0 

Truth table 

(Pending – table)

Working 

• According to the truth table, when I1I0=00, the output Y0 is set to ‘1’, others are‘0’ 
• When I1I0=01, the output Y1 is set to ‘1’, others are ‘0’ 
• Similarly, for other input combinations, particular output is set to ‘1’ & others are‘0
  

3 to 8 Decoder

Block diagram 

(Pending – diagram)

Truth Table

(Pending- table)

Working 

• According to the truth table, when  When I2I1I0=001, the output Y0 is set to ‘1’, others are‘0’ 
• When I2I1I0=000, the output the output Y1 is set to ‘1’, others are‘0’ 
• Similarly, for other input combinations, particular output is set to ‘1’ & others are‘0’ 

Boolean Equation:

            Y0= I̅2I̅1I̅0;            Y1= I̅2I̅1I0;                          Y2= I̅2I1I̅0;             Y3= I̅2I1I0                          Y4= I2I̅1I̅0;             Y5= I2I̅1I0;                          Y6= I2I1 I̅0;            Y7= I2I1I0;

Circuit Diagram 

(Pending – diagram)

(Pending- Post MCQ)