1. Why PCIe is a serial Protocol?
PCIe is a serial protocol because it sends data one bit at a time, as opposed to parallel protocols, which send data multiple bits at a time.
There are a number of reasons why PCIe is a serial protocol:
Speed: Serial protocols can achieve higher speeds than parallel protocols. This is because serial protocols are less susceptible to crosstalk, which is a phenomenon that occurs when signals on adjacent wires interfere with each other.
Cost: Serial protocols are less expensive to implement than parallel protocols. This is because serial protocols require fewer wires and connectors.
Power consumption: Serial protocols consume less power than parallel protocols. This is because serial protocols only need to drive one wire at a time, while parallel protocols need to drive multiple wires at a time.
2. Why do we use scrambling in PCIe?
There are two main reasons why scrambling is used in PCIe:
To reduce the possibility of electrical resonances on the link. PCI Express is a high-speed serial protocol, and as such, it is susceptible to electrical resonances. Electrical resonances can occur when the length of the transmission line matches the wavelength of the signal. This can cause the signal to be reflected back and forth, which can lead to errors. Scrambling helps to reduce the possibility of electrical resonances by randomizing the signal.
To improve the performance of equalization. Equalization is a technique that is used to compensate for the effects of attenuation and distortion on the signal. Scrambling helps to improve the performance of equalization by making the signal more predictable.
3. Why do we use 8b/10b or 128b/130b encoding in PCIe Gen 3 or Gen 4?
We use 8b/10b or 128b/130b encoding in PCIe Gen 3 or Gen 4 because it provides a number of benefits, including:
DC balance: 8b/10b and 128b/130b encoding ensure that the DC balance of the signal is maintained. This means that the number of positive and negative pulses on the signal is equal. This is important because it helps to reduce EMI and improve the reliability of the signal.
Bounded disparity: 8b/10b and 128b/130b encoding ensure that the disparity of the signal is bounded. This means that the difference between the number of positive and negative pulses on the signal is limited. This is important because it helps to prevent errors from occurring.
Clock recovery: 8b/10b and 128b/130b encoding provide enough transitions in the signal to allow for clock recovery. This is important because it allows the receiver to synchronize its clock with the sender’s clock.
4. Which symbols are not scrambled in PCIe?
The following symbols are not scrambled in PCIe:
COM: The COM symbol is used to signal the start of a communication sequence.
IDLE: The IDLE symbol is used to indicate that the lane is idle.
SKP: The SKP symbol is used to skip a symbol in the data stream.
Training sequence: The training sequence is used to calibrate the PCIe link.
5. When is scrambling re-started?
Scrambling is re-started in the following cases:
When the link enters reset.
When a link error occurs.
When the link speed is changed.
When a link training procedure is completed.
When the link is configured to use a different scrambling algorithm.
Scrambling is also re-started when the link enters a low-power state. This is done to prevent the link from becoming desynchronized.
6. What is difference between pre-emphasis and de-emphasis?
Pre-emphasis and de-emphasis are complementary techniques used to improve the signal-to-noise ratio (SNR) of communication systems.
Pre-emphasis is the process of boosting the high-frequency components of a signal before transmission. This compensates for the high-frequency attenuation that occurs in transmission lines and other components. Pre-emphasis can be implemented using a variety of techniques, such as filters and equalizers.
De-emphasis is the process of reducing the high-frequency components of a signal after reception. This compensates for the pre-emphasis that was applied at the transmitter. De-emphasis can also be implemented using a variety of techniques, such as filters and equalizers.
The difference between pre-emphasis and de-emphasis is that pre-emphasis is applied at the transmitter, while de-emphasis is applied at the receiver. Pre-emphasis is used to boost the high-frequency components of a signal, while de-emphasis is used to reduce the high-frequency components of a signal.
7. Difference between logical idle and electrical idle?
Logical idle and electrical idle are two different states that a PCI Express (PCIe) link can be in.
Logical idle is a state where the transmitter is sending idle symbols, but the link is still active. This means that the receiver can still detect the clock and symbol lock. Logical idle is used to indicate to the receiver that there is no data to be transmitted, but the link should remain active.
Electrical idle is a state where the transmitter is not sending any signals, and the link is inactive. This means that the receiver cannot detect the clock or symbol lock. Electrical idle is used to save power when the link is not in use.
8. Difference between PAD and IDL?
If a packet doesn’t end on the last Lane of the Link and there are no more packets ready to go, PAD Symbols are used as filler on the remaining lane numbers. Logical Idle can’t be used for this purpose because it must appear on all Lanes at the same time
9. Why SKP is ignored by scrambler?
Except for the COM character, the LFSR normally will serially advance eight times for every D or K character sent, but it does not advance on SKP characters associated with the SKIP ordered set. The reason is that a receiver may add or delete SKP Symbols to perform clock tolerance compensation. Changing the number of characters in the receiver compared to the number that were sent would cause the value in the receiver LFSR to lose synchronization with the transmitter LFSR value if they were not
ignored.
10. Why do we need Tx or Rx buffers in Physical Layer of PCIe?
Tx buffer accepts TLPs and DLLPs from the Data Link Layer, along with ‘Control’ information that specifies when a new packet begins. Buffer allows us to stall the flow of characters from time to time in order to insert control characters and ordered sets. A ‘throttle’ signal is also shown going back up to the Data Link Layer to stop the flow of characters if the buffer should become full.
The Rx Buffer holds received TLPs and DLLPs until the Data Link Layer is able to accept them.
11. What is significance of elastic buffer in PCIe physical layer?
The Elastic Buffer compensates for the frequency difference by adding or removing SKP Symbols. When a SKP ordered set arrives, logic watching the status of the elastic buffer makes an evaluation. If the local clock is running faster, Symbols are being clocked out faster than they’re coming in, so the buffer will be approaching an underflow condition. The logic will compensate for this by appending an extra SKP Symbol to the ordered set when it arrives to quickly refill the buffer. On the other hand, if the recovered clock is running faster, the buffer will be approaching an overflow condition and the logic will compensate for that by deleting one of the SKP Symbols to quickly drain the buffer. These actions will make up for difference in rates of arrival and consumption of the Symbols and prevent any confusion or loss of data.
12. Why do we need to replicate Ordered Sets on all lanes?
Ordered-Sets are replicated on all Lanes at the same time, because each Lane is technically an independent serial path. This also allows Receivers to verify alignment and de‐skewing.
13. What is DC balance?
PCIe uses an AC‐coupled link, placing a capacitor serially in the path to isolate the DC part of the signal from the other end of the Link. This allows the Transmitter and Receiver to use different common‐mode voltages and makes the electrical design easier for cases where the path between them is long enough that they’re less likely to have exactly the same reference voltages. That DC value, or common‐mode voltage, can change during run time because the line charges up when the signal is driven. Normally, the signal changes so quickly that there isn’t time for this to cause a problem but, if the signal average is predominantly one level or the other, the common mode value will appear to drift. Referred to as “DC Wander”, this drifting voltage degrades signal integrity at the Receiver.