Applying the following ensures the timing closure of any design:
–> Timing Constraints
–> CDC Constraints
–> STA Analysis
–> CDC Techniques
Timing closure is an essential part of a design(ASIC/SoC) in-order to meet the expected functional behavior of design in both simulation and in real hardware (silicon). Below are the functional issues that require attention by design engineers to avoid chip scrap at a later stage.
# Data Corruption:
When the input data changes very close to the flop input where the data doesn’t meet the timing requirements of a flop such as setup time, the flop likely to store an incorrect data for the correspond operation, that leads to data corruption.
# Meta-stability:
Meta-stability affects the subsequent logic in a design, as the data might get settled down in an unknown state between (0 or 1), this occurs when there is input data of a flop changes at the clock transition, the data likely to go into a unknown state, meta-stability issues could be resolved by giving enough time to settle the data to an known state from an unknown state, before allowing it to traverse to the subsequent logic in a design.
# Setup and Hold Violations:
Improper timing closure leads to setup and hold timing violations at flops, it primarily happens where the data changes too close to the active-edge of the clock by not providing enough time before and after active clock-edge and to capture the appropriate data. Setup and hold timing violations causes functional issues of design, and require proper constraints/fixes for proper functioning.
# Race Conditions:
Race conditions occur where there are event changes at the same time and update the same signal, for the proper functioning the same signal should get update during different timing interval, due to improper timing closure, the timing control events can occur at any interval, which makes the timing behavior of the design unpredictable or non-deterministic.
# Glitches and Transients:
Glitches occur due to improper timing closure in combinational logic, it introduces short pulses in the signal transitions, this short pulse can cause an unexpected behavior in down the logic, In short glitches can affect the functional behavior of a design and it requires proper timing closure.
# Incorrect control or state machine operations:
Timing closure links to the state transitions of control signals in a state machine, which may lead to improper state (FSM states) changes in the operation, and it leads to improper functional behavior of a design.