In our executive overview of the PCIe architecture, we learned that data transmission is divided into distinct functional layers. Now, we dive deeply into the Transaction Layer, the intelligence engine located just below the device’s core logic. This layer is primarily responsible for the creation of outbound Transaction Layer Packets (TLPs) and the decoding of inbound TLPs.
Here is a detailed look at how the Transaction Layer acts as an assembly line, packaging the system’s demands into perfectly formatted TLPs ready for transmission.
The Four Categories of PCIe Requests
Whenever the software or the device core needs to interact with the system, the Transaction Layer translates that need into one of four distinct request categories:
- Memory Requests: The most common transaction, used to read from or write to system RAM or memory-mapped device buffers.
- IO Requests: Used strictly for legacy support to communicate with older devices that still rely on legacy IO address space.
- Configuration Requests: Used strictly by the Root Complex to discover devices, configure their registers, and assign them addresses during system boot.
- Message Requests: A massive innovation in PCIe. Instead of using dedicated physical wires (side-band signals) for things like interrupts or error reporting, PCIe sends “virtual wires” in the form of in-band Message TLPs.
The TLP Assembly Line: How Packets are Created
When an application or a device driver decides it needs to move data, the Transaction Layer springs into action. Let’s walk through the creation of a standard request (like a Memory Read) step-by-step:
1. Instructions from the Device Core (Software Layer) The process begins at the top. The Device Core (often referred to as the Software Layer) hands the Transaction Layer the raw ingredients for the transaction. This includes the transaction type, the target address (32-bit or 64-bit), the amount of data to transfer, and the assigned Traffic Class (priority).
2. Building the TLP Header The Transaction Layer takes these raw ingredients and constructs the TLP Header.
- Header Size: If the transaction targets an address below 4GB, it uses a 32-bit address and builds a 3-Doubleword (12-byte) header. If the transaction targets an address above 4GB, it requires a 64-bit address and the layer builds a 4-Doubleword (16-byte) header.
- Routing Information: The header includes the target address or ID so the packet can be routed through Switches. It also includes the Requester ID (the device’s unique Bus, Device, and Function number) so the target device knows exactly where to send the Completion data back.
3. Adding the Payload and ECRC If the transaction is a write operation, the data payload is appended directly after the header. Finally, the Transaction Layer has the option to calculate and append an End-to-End CRC (ECRC). This is a crucial security feature: because the ECRC remains completely unchanged as the packet is routed through intermediate Switches, the final target device can use it to verify that the packet’s core contents were not corrupted anywhere along its journey through the PCIe fabric.
Traffic Management: Virtual Channels and Flow Control
Once the TLP is fully assembled, it doesn’t just blindly blast out onto the physical wire. The Transaction Layer is heavily involved in traffic management.
The newly created TLP is placed into a specific transmit buffer called a Virtual Channel (VC) based on its assigned priority. Before the packet is allowed to move down to the next layer, the Transaction Layer’s Flow Control logic checks the status of the neighboring device. It verifies that the receiving device has explicitly advertised that it has enough available buffer space to accept this specific TLP.
Only when sufficient buffer space is confirmed will the Transaction Layer release the packet, passing it down to the Data Link Layer to be prepped for its physical journey across the Link.