As we learned in previous modules, the legacy parallel PCI and PCI-X buses eventually hit physical performance ceilings due to strict timing budgets, clock skew, and signal flight time limitations. To overcome these insurmountable physical barriers, the industry made a revolutionary architectural shift with PCI Express (PCIe): abandoning the shared parallel bus in favor of a high-speed serial interconnect.
Here is a look at how this serial transport model completely reimagined data transfer to achieve unprecedented speeds.
The Dual-Simplex Connection: Simultaneous Transmit and Receive
Unlike the legacy PCI bus where multiple devices shared a single central pathway and had to take turns transmitting, PCIe utilizes a dedicated point-to-point connection between two devices.
This connection operates on a dual-simplex architecture. This means that each PCIe interface contains a dedicated simplex transmit path and a separate simplex receive path. Because data can travel in both directions simultaneously, the communication path between the two devices is technically full-duplex.
In PCIe terminology, the complete physical connection between two devices is called a Link. This Link is constructed from one or more Lanes, where a single Lane consists of exactly one differential transmit signal pair and one differential receive signal pair.
Solving the Parallel Problem: Flight Time and Clock Skew
In a parallel bus design, a common (or distributed) clock is shared by all devices. The transmitter drives data out on one clock edge, and the receiver latches it on the very next clock edge. This introduces two massive problems as speeds increase:
- Flight Time: The actual time it takes for the signal to physically travel down the wire (flight time) must be strictly less than the clock period. As clock frequencies increase and periods shrink, trace lengths must become impractically short to beat the clock.
- Clock Skew: The common clock rarely arrives at the transmitter and the receiver at the exact same picosecond, eating into the already tiny timing budget.
Breaking the Speed Barrier by Embedding the Clock
PCIe elegantly solves both of these problems by completely eliminating the need for a common external reference clock to latch the data.
Instead of relying on a separate clock signal, the PCIe transmitter embeds the clock directly into the data stream itself. It does this using specialized data encoding schemes, such as 8b/10b encoding (for Gen1 and Gen2 speeds) or 128b/130b encoding (for Gen3).
When the serial data arrives at the receiver, a specialized circuit called a Phase-Locked Loop (PLL) takes the incoming bit stream and uses it as a reference to automatically recover the clock. The receiver then uses this newly recovered clock to reliably latch the incoming data.
By embedding the clock directly into the data stream, PCIe entirely eliminates the legacy limitations of parallel buses:
- Flight time becomes a non-issue: It no longer matters how long it takes for the signal to physically travel from point A to point B, because the latching clock arrives at the exact same time as the data.
- Clock skew is eliminated: Since the latching clock is recovered directly from the individual data stream rather than a separate central wire, clock skew between devices is effectively removed from the equation.
By shifting to a dual-simplex serial design with an embedded clock, PCI Express shattered the speed ceilings of parallel buses, paving the way for the massive bandwidth scaling we see in modern computer architecture.