As we explored in our previous module on the evolution of peripheral buses, the PCI bus transformed the PC landscape. But to fully appreciate how modern systems evolved, we must first understand exactly how this legacy architecture operates under the hood. Here is a breakdown of the foundational PCI architecture, the roles of initiators and targets, and the anatomy of a standard PCI bus cycle.
The Shared Parallel Bus Model
In a traditional legacy PCI-based system, the architecture revolves around a centralized, shared bus. The system features a North Bridge that acts as the critical interface between the system’s processor, memory, and the central PCI bus. Multiple devices share this single PCI bus, either integrated directly onto the motherboard or inserted into add-in card slots.
Further downstream, a South Bridge connects the PCI bus to slower, legacy system peripherals (like ISA devices) and typically provides central system signals, including the reference clock, reset, and the central bus arbiter.
Initiators (Bus Masters) and Targets
Every device function on a PCI bus is capable of acting as a target to receive transactions. However, most modern devices also have the intelligence to initiate transactions themselves; these devices are known as initiators or Bus Masters.
Because the PCI bus is a shared parallel pathway, only one Bus Master can communicate at a time. To prevent chaos, devices must take turns using a strict arbitration process:
- Requesting the Bus: When a Bus Master needs to transfer data, it asserts a dedicated Request (REQ#) pin to signal the central bus arbiter.
- Granting the Bus: The arbiter evaluates all pending requests and decides which device gets to go next, asserting that specific device’s Grant (GNT#) pin.
- Taking Ownership: As soon as the previous transaction finishes and the bus goes idle, the device that sees an active GNT# signal instantly becomes the next Bus Master and can begin its transfer.
How a Typical Synchronous PCI Bus Cycle Operates
PCI is a synchronous bus, meaning all signal transfers and events are tightly coordinated to the rising edges of a shared system clock. Transactions are managed using a set of multiplexed Address/Data (AD) pins and specific handshake control signals.
Here is the step-by-step lifecycle of a typical PCI read transaction:
- Starting the Transaction: When the bus is idle, the selected Bus Master asserts the FRAME# signal to announce that a new transaction is beginning. At the exact same time, it drives the target address and the specific command onto the bus. Every other device on the bus latches this information to decode whether they are the intended target.
- Claiming the Cycle: The target device recognizes its address and responds by asserting DEVSEL# (Device Select), officially claiming the transaction and agreeing to participate.
- The Turn-Around Cycle: Because the 32 address and data signals share the exact same physical pins to save cost, a read transaction requires a “turn-around cycle”. The initiator must turn off its transmit buffers one clock edge before the target turns its buffers on, preventing a scenario where both devices drive voltage onto the same wire simultaneously, which could cause hardware damage.
- Data Transfer (The Handshake): Data only successfully moves across the bus when both parties are ready. The initiator asserts IRDY# (Initiator Ready) to show it is prepared to receive data, and the target asserts TRDY# (Target Ready) to show it is delivering the data. When both IRDY# and TRDY# are active on the same clock edge, a data phase is completed, and the bytes are transferred.
- Inserting Wait States: If either the initiator or the target needs a moment to process data or clear a buffer, they can deassert their respective ready signal (IRDY# or TRDY#). This inserts a “Wait State”, pausing the transaction for a clock cycle. While this prevents the transaction from needing to be completely restarted, excessive Wait States are highly inefficient because they stall the entire shared bus, blocking other devices from communicating.
- Transaction Completion: In the PCI protocol, the target does not know in advance how many bytes the initiator wants to read. Therefore, the target must constantly monitor the FRAME# signal. When the initiator is on its final data phase and is satisfied with the amount of data, it deasserts FRAME#. After this final transfer, all control lines are turned off, and the bus returns to an idle state, ready for the next Bus Master