When data is transferred across a PCIe (Peripheral Component Interconnect Express) interface, it is not always a full 32-bit or 64-bit word. To specify which bytes within a data word are valid or should be written/read, the Byte Enable fields are used.
Let’s go step by step through the rules governing byte enables and understand their purpose.
1. Byte Enable Polarity
- Byte enable bits are active-high.
- ‘1’ means the corresponding byte in the data payload is valid and should be used.
- ‘0’ means that byte is invalid or ignored by the Completer (the device receiving the transaction).
🧠 Example:
For a 32-bit (4-byte) data word, a Byte Enable value of 1111b means all four bytes are valid.
A value of 1100b means only the upper two bytes are valid.
2. Single DW Transfers
If all valid data fits within a single Double Word (DW):
- The Last DW Byte Enable must be set to 0000b.
- Only the First DW Byte Enable field defines which bytes are valid.
🧩 Why?
There is no “last” DW in a single-DW transfer, so the field must remain 0.
3. Multi-DW Transfers (More than 1 DW)
For any transfer larger than one DW, the First DW Byte Enable must have at least one bit set (i.e., it can’t be 0000b).
💡 Meaning:
Even if the data doesn’t start at the first byte, at least one valid byte must exist in the first DW to mark the start boundary of the transfer.
4. Transfers of 3 DW or More
When the Length field shows a transfer of 3 DWs or more, then:
- Both First DW and Last DW Byte Enable fields must have contiguous bits set.
⚙️ Purpose:
In large transfers, these fields define the byte offset of the start and end addresses.
This ensures that the data stream is continuous and aligned properly from the beginning to the end.
5. Discontinuous Byte Enables for 1 DW
When the transfer length is exactly 1 DW, discontinuous byte enable patterns are allowed.
🧠 Example:
1010b is valid for a single DW write — meaning only bytes 1 and 3 are active.
6. Discontinuous Enables for 1–2 DWs
If the transfer length is between one and two DWs, both First and Second DW Byte Enables can have non-contiguous patterns.
🔍 Reason:
This allows partial updates across a small range, often used in memory-mapped I/O operations where not all bytes are required.
7. 1 DW Write with No Enables
If a 1 DW write request has no byte enables set (0000b):
- It is considered legal but performs no operation on the Completer.
🧱 This is sometimes used as a “dummy” write that doesn’t modify data but still follows PCIe transaction rules.
8. 1 DW Read with No Enables (Flush Mechanism)
If a 1 DW read request has no byte enables set:
- The Completer returns undefined data (the payload content is meaningless).
- This type of read can be used as a Flush operation to enforce transaction ordering.
⚙️ Practical Use:
It ensures that all previously posted writes are completed before this completion is issued — effectively acting as a synchronization point in PCIe systems.
Summary Table
| Condition | Description | Valid Byte Enable Behavior |
| 1 DW Transfer | No Last DW BE used | Last DW BE = 0000b |
| >1 DW Transfer | First DW BE must have valid bits | At least one bit = 1 |
| ≥3 DW Transfer | Both BE fields contiguous | No gaps allowed |
| 1 DW Transfer | Discontinuous BE allowed | e.g., 1010b |
| 1–2 DW Transfer | Discontinuous BE in both DWs allowed | Flexible |
| 1 DW Write, 0000b | No effect | Legal, no operation |
| 1 DW Read, 0000b | Flush operation | Undefined data returned |
Conclusion
Byte Enable rules are crucial in PCIe to ensure that partial data transfers are correctly interpreted by both Requester and Completer. They optimize bus usage, define data boundaries precisely, and maintain transaction ordering integrity.