SEQUENTIAL MODELS
In digital circuits, storage of data is done either by feedback, or by gate capacitances
that are refreshed frequently.
Pending : Fig.181 Sequential models
FEEDBACK MODEL:
Pending : Fig.182 Feedback Mode
CAPACITIVE MODEL
Pending : Fig.183Capacitive model
When c becomes 1 the value of D is saved in the input gate of the inverter and when c
becomes 0 this value will be saved until the next time that c becomes 1 again.
IMPLICIT MODEL
Pending : Fig.184 Implicit model
Feedback and capacitive models are technology dependent and have the problem of
being too detailed and too slow to simulate. Verilog offers language constructs that are
technology independent and allow much more efficient simulation of circuits with a large
number of storage elements.
BASIC MEMORY COMPONENTS
Pending : Fig.185 Basic Memory components
GATE LEVEL PRIMITIVES
Pending : Fig.186 Basic Latch
Example 38: Basic Latch
`timescale 1ns/100ps
module latch (input s, r, output q, q_b );
nor #(4)
g1 ( q_b, s, q ),
g2 ( q, r, q_b );
endmodule
q and q_b outputs are initially X and remain at this ambiguous state for as long as s
and r remain 0. Simultaneous assertion of both inputs results in loss of memory.
Pending : Fig.187 Latch with parameters
Example 39: Latch with Parameters
`timescale 1ns/100ps
module latch_p #(parameter tplh=3, tphl=5) (input s, r, c, output q, q_b );
wire _s, _r;
nand #(tplh,tphl)
g1 ( _s, s, c ),
g2 ( _r, r, c ),
g3 ( q, _s, q_b ),
g4 ( q_b, _r, q );
endmodule
Pending : Fig.188 Output waveforms for latch
Pending : Fig.189 Master slave flip-flop
Example 40: Master slave flip-flop
`timescale 1ns/100ps
module master_slave (input d, c, output q, q_b );
wire qm, qm_b;
defparam master.tplh=4, master.tphl=4, slave.tplh=4, slave.tphl=4;
latch_p
master ( d, ~d, c, qm, qm_b ),
slave ( qm, qm_b, ~c, q, q_b );
endmodule
USER DEFINED SEQUENTIAL PRIMITIVES
Verilog provides language constructs for defining sequential UDPs:
Faster Simulation of memory elements
Correspondence to specific component libraries
Example 41: Latch primitive
primitive latch( q, s, r, c );
output q;
reg q;
input s, r, c;
initial q=1’b0;
table
// s r c q q+ ;
// ——:—:—-;
? ? 0 : ? : – ;
0 0 1 : ? : – ;
0 1 1 : ? : 0 ;
1 0 1 : ? : 1 ;
endtable
endprimitive
primitive latch( q, s, r, c );
table
// s r c q q+ ;
// ——:—:—-;
? ? 0 : ? : – ;
0 0 1 : ? : – ;
0 1 1 : ? : 0 ;
1 0 1 : ? : 1 ;
endtable
endprimitive
MEMORY ELEMENTS USING ASSIGNMENTS
When a block’s clock input is 0, it puts its output back to itself (feedback), and when
its clock is 1it puts its data input into its output.
Example 42:
`timescale 1ns/100ps
module master_slave_p #(parameter delay=3)
(input d, c, output q);
wire qm;
assign #(delay) qm = c ? d : qm;
assign #(delay) q = ~c ? qm : q;
endmodule
Pending : Fig.190 Master Slave Flip-flop
BEHAVIORAL MEMORY ELEMENTS
Behavioral Coding:
A more abstract and easier way of writing Verilog code for a latch or flip-flop.
The storage of data and its sensitivity to its clock and other control inputs will be implied
in the way model is written.
Pending : Fig.191 Behavioral Memory Elements
LATCH MODELING
Example 43: A latch
`timescale 1ns/100ps
module latch (input d, c, output reg q, q_b );
always @( c or d )
if ( c )
begin
#4 q = d;
#3 q_b = ~d;
end
endmodule
`timescale 1ns/100ps
module latch (input d, c, output reg q, q_b );
always @( c or d )
if ( c )
begin
q <= #4 d;
q_b <= #3 ~d;
end
endmodule
FLIP-FLOP MODELING
Example 44:
`timescale 1ns/100ps
module d_ff (input d, clk, output reg q, q_b );
always @( posedge clk )
begin
q <= #4 d;
q_b <= #3 ~d;
end
endmodule
FLIP-FLOP WITH SET-RESET CONTROL
Example 45:
`timescale 1ns/100ps
module d_ff_sr_Synch (input d, s, r, clk, output reg q, q_b );
always @(posedge clk) begin
if( s ) begin
q <= #4 1’b1;
q_b <= #3 1’b0;
end else if( r ) begin
q <= #4 1’b0;
q_b <= #3 1’b1;
end else begin
q <= #4 d;
q_b <= #3 ~d;
end
end
endmodule
module d_ff_sr_Synch (input d, s, r, clk,
output reg q, q_b );
always @(posedge clk) begin
if( s ) begin
……………..
end else if( r ) begin
……………..
end else begin
……………..
end
end
endmodule
………………
if( s ) begin
q <= #4 1’b1;
q_b <= #3 1’b0;
end else if( r ) begin
q <= #4 1’b0;
q_b <= #3 1’b1;
end else begin
q <= #4 d;
q_b <= #3 ~d;
end
………………
`timescale 1ns/100ps
module d_ff_sr_Asynch (input d, s, r, clk, output reg q, q_b );
always @( posedge clk, posedge s, posedge r )
begin
if( s ) begin
q <= #4 1’b1;
q_b <= #3 1’b0;
end else if( r ) begin
q <= #4 1’b0;
q_b <= #3 1’b1;
end else begin
q <= #4 d;
q_b <= #3 ~d;
end
end
endmodule
module d_ff_sr_Asynch (input d, s, r, clk,
output reg q, q_b );
always @( posedge clk, posedge s, posedge r ) begin
if( s ) begin
………………..
end else if( r ) begin
………………..
end else begin
………………..
end
end
endmodule
………………..
if( s ) begin
q <= #4 1’b1;
q_b <= #3 1’b0;
end else if( r ) begin
q <= #4 1’b0;
q_b <= #3 1’b1;
end else begin
q <= #4 d;
q_b <= #3 ~d;
end
………………..
OTHER STORAGE ELEMENT MODELING STYLES
Example 46:
`timescale 1ns/100ps
module latch (input d, c, output reg q, q_b );
always begin
wait ( c );
#4 q <= d;
#3 q_b <= ~d;
end
endmodule
FLIP-FLOP TIMING
Pending : Fig.192 Flip-flop Timing
Setup Time
The Minimum necessary time that a data input requires to setup before it is clocked into a
flip-flop.
Verilog construct for checking the setup time: $setup task
The $setup task:
Takes flip-flop data input, active clock edge and the setup time as its parameters.
Is used within a specify block.
Ex: specify
$setup (d, posedge clk, 5);
endspecify
Hold Time
The Minimum necessary time a flip-flop data input must stay stable (holds its value)
after it is clocked.
Verilog construct for checking the setup time: $hold task
The $setup task:
Takes flip-flop data input, active clock edge and the required hold time as its parameters.
Is used within a specify block.
Ex: specify
$hold ( posedge clk, d, 3 );
endspecify
The Verilog $setuphold task combines setup and hold timing checks.
Ex: $setuphold (posedge clk, d, 5, 3);
Width And Period
Verilog $width and $period check for minimum pulse width and period.
Pulse Width: Checks the time from a specified edge of a reference signal to its opposite
edge.
Period: Checks the time from a specified edge of a reference signal to the same edge.
EX: specify
$setuphold ( posedge clk, d, 5, 3 );
$width (posedge r, 4);
$width (posedge s, 4);
$period (negedge clk, 43);
endspecify
FUNCTIONAL REGISTER
SHIFT REGISTERS
Pending : Fig. 193 Basic Shift Register
COUNTERS
Pending : Fig.194 Grey Code Counter
STATE MACHINE CODING
Pending : Fig.194 State Machine Coding
Moore Machine :
A state machine in which all outputs are carefully synchronized with the circuit clock.
In the state diagram form, each state of the machine specifies its outputs independent of
circuit inputs.
In Verilog code of a state machine, only circuit state variables participate in the output
expression of the circuit.
Mealy Machine :
Is different from a Moore machine in that its output depends on its current state and
inputs while in that state.
State transitions and clocking and resetting the machine are no different from those of a
Moore machine. The same coding techniques are used.