INTRODUCTION
Digital designers are normally familiar with all the common logic gates, their symbols, and their working. Flip-flops are built from the logic gates. All other functionally complex and more involved circuits can also be built using the basic gates. All the basic gates are available as “Primitives” in Verilog. Primitives are generalized modules that already exist in Verilog. They can be instantiated directly in other modules. Further design description using gate primitives is quite close to the actual circuits.
AND Gate Primitive
The AND gate primitive in Verilog is instantiated with the following statement:
and g1 (O, 11, 12, . . ., In);
Here ‘and’ is the keyword signifying an AND gate. g1 is the name assigned to the specific instantiation. O is the gate output; 11, 12, etc., are the gate inputs. The following are noteworthy:
- The AND module has only one output. The first port in the argument list is the output port.
- An AND gate instantiation can take any number of inputs – the upper limit is compiler specific.
- A name need not be necessarily assigned to the AND gate instantiation; this is true of all
the gate primitives available in Verilog
Example 1
Fig.1 shows the stimulus program for testing the AND gate g1. The out put obtained by stimulating the program is shown in Fig.2. Some explanation regarding the simulation program is in order here.
The module test_and has no port. It instantiates the AND module once.
The test input sequence is specified within the initial block – the sequence of statements between the begin and end statements together form this block.
The keyword “initial” signifies the settings done initially — that is, only once for the
whole routine.
The first set of statements within the initial block
a1 = 0;
a2 = 0;
make
a1 = a2 = 0
at zero simulation time.
• After 3 time steps, a1 is set to one but a2 remains at 0. The expression “#3” means “after 3 time steps”. Subsequent changes in a1 and a2 also can be explained in the same manner
Pending : Fig.1 A Module to instantiate AND gate Primitive
Pending : Fig.2 Output of the Module shown in fig.1
- The program displays the variable values – that is, the values of O, a1, and a2 whenever
any one of these changes. This is evident from the printout on the monitor, which has
been reproduced in Fig.2. - A pair of variables a1 and a2 are declared in the program, and the values stored in them are given as inputs to the AND gate instantiation.
- Any variable not declared in the module is by default taken as a net of wire type; it is also taken as a scalar. The same is true of all modules in Verilog.
- The term $time in the $monitor statement signifies the running time of the program. Here it causes the value of time at the instant of capturing the data for display, to be displayed.
- The statement #100 $finish; Signifies that the program will stop simulation and exit the operating system at the end of 100 time steps.
Truth Table of AND Gate Primitive
The truth table for a two-input AND gate is shown in Table 1. It can be directly extended to AND gate instantiations with multiple inputs. The following observations are in order here:
Pending : Table 1 Truth Table of AND gate Primitive
- If any one of the inputs to the AND gate instantiation is in the 0 state, its output is also in the 0 state. It is irrespective of whether the other inputs are at the 0, l ,xor z state.
- The output is at 1 state if and only if every one of the inputs is at 1 state.
- For all other cases the output is at the x state.
- Note that the output is never at the z state – the high impedance state. This is true of all other gate primitives as well.
MODULE STRUCTURE
Fig.1 shows a typical module. In a general case a module can be more elaborate. A lot of flexibility is available in the definition of the body of the module. However, a few rules need to be followed:
- The first statement of a module starts with the keyword module; it may be followed by
the name of the module and the port list if any. - All the variables in the ports-list are to be identified as inputs, outputs, or inouts. The
corresponding declarations have the form shown below:
• Input a1,a2;
• Output b1, b2;
• Inout c1, c2; - The port-type declarations here follow the module declaration mentioned above.
- The ports and the other variables used within the body of the module are to be identified as nets or registers with specific types in each case. The respective declaration statements follow the port-type declaration statements.
Examples:
wire a1, a2 , c;
reg b1, b2 ;
The type declaration must necessarily precede the first use of any variable or signal in the
module. - The executable body of the module follows the declaration indicated above.
- The last statement in any module definition is the keyword “endmodule”.
- Comments can appear anywhere in the module definition.
OTHER GATE PRIMITIVES
All other basic gates are also available as primitives in Verilog. Details of the facilities and instantiations in each case are given in Table 2. The following points are noteworthy here:
- In all cases of instantiations, one need not necessarily assign a name to the instantiation. It need be done only when felt necessary — say for clarity of circuit description.
- In all the cases the output port(s) is (are) declared first and the input port(s) is (are) declared subsequently.
- The buffer and the inverter have only one input each. They can have any number of outputs; the upper limit is compiler-specific. All other gates have one output each but can have any number of inputs; the upper limit is again compiler-specific.
- Pending : Table 2 Basic gate primitives in Verilog with details
Truth Table
Extending the concepts of truth table of the AND gate primitive, one can form the truth tables of all other gate primitives. The basic features of each are given in Table 3.
Pending : Table 3 Rules for deciding the output values of gate primitives for different input combinations
Pending : 5. ILLUSTRATIVE EXAMPLES
TRI-STATE GATES
Four types of tri-state buffers are available in Verilog as primitives. Their outputs can be turned ON or OFF by a control signal. The direct buffer is instantiated as
Bufiflnn (out, in, control);
The symbol of the buffer is shown in Fig.20.
Pending : Fig.20 A tri–state Buffer
We have
- out as the single output variable
- in as the single input variable and
- control as the single control signal variable.
When control = 1,
out = in.
When control = 0,
out is cut off from the input and tri-stated. The output, input and control signals should appear in the instantiation in the same order as above. Details of bufifl as well as the other tri-state type primitives are shown in Table 4. In all the cases shown in Table 4, out is the output, in is the input, and control, the control variable.
The following observations are common to all the tri-state buffer primitives:
- If the control signal has a value that corresponds to the buffer being on, two possibilities exist:
The output has the same value as the input if the input is 0 or 1.
The output is at x otherwise (i.e., if the input is x or z). - If the control signal has a value that corresponds to the control signal being off, the
output is at z state irrespective of the value of the input. - If the control signal is at x or z, three possibilities arise:
If the input is at x or z, the output is at x.
If the input is at 0 state, the output is L for bufifl and bufifO. It is at H for
notifl and notifO.
If the input is at 1 state, the output is H for bufifl and bufifO. It is at L for
notifl and notifO.
Note that H corresponds to 1 or z state while L corresponds to 0 or z state.
Pending : Table 4 Instantiation and functional details of tri-state buffer primitives
ARRAY OF INSTANCES OF PRIMITIVES
The primitives available in Verilog can also be instantiated as arrays. A judicious use of such array instantiations often leads to compact design descriptions. A typical array instantiation has the form
and gate [7:4] (a, b, c);
Where a, b, and C are to be 4 bit vectors. The above instantiation is equivalent to combining the following 4 instantiations:
and gate [7] (a[3], b[3], c[3]), gate [6] (a[2], b[2], c[2]), gate [5] (a[1], b[1], c[1 ]), gate [4]
(a[0], b[0], c[0]);
The assignment of different bits of input vectors to respective gates is implicit in the basic declaration itself. A more general instantiation of array type has the form
and gate [mm:nn] (a, b, c);
Where mm and nn can be expressions involving previously defined parameters, integers and algebra with them. The range for the gate is 1+ (mm-nn); mm and nn do not have restrictions of sign; either can be larger than the other.
Example 4: A Byte Comparator
A circuit to compare two variables each of one byte is given in Fig.21. The circuit outputs a flag d; d is 1 if the two bytes are equal; else it is 0. The output is activated only ifthe enable signal en = 1. If en = 0, the circuit output is tri-stated. The module description is given in Fig.22 along with a testbench. The simulated output is in Fig.23.
Pending : Fig.21 A byte Comparator
Observations:
- In all array-type instantiations, the array sizes are to be matched.
- The order of assignments to outputs, inputs, etc., in the individual gates will be decided by the order of the bits. Thus the array instantiation
Or gg [3:1] (a[3:1 ], b[4:2], c); - is equivalent to the combination of instantiations
or gg [3] (a[3], b[4], c[2]), gg[2] (a[2], b[3], c[1]), gg[1] (a[1], b[2], c[0]); - If the vector sizes in the port list do not match the array size specified, assignments will be done starting from the right; that is, the rightmost instantiation will be assigned the rightmost inputs and outputs and the following instantiations will be made assignments in the order specified. However, it is desirable to avoid such ill-matched instantiations.
- In the general case the array size is specified in terms of two constant expressions. These can involve constants, previously defined parameters and algebraic operators: Such an instantiation can have a form as
and gate [offset*2+size-1: offset*2] (a, b, c);
Where ‘offset’ and ‘size’ are parameters whose values should have been assigned earlier. - Pending : Fig.22 Module of an 8 – bit comparator and its test bench
- Pending : Fig.23 Results of test bench for 8-bit comparator
DESIGN OF FLIP-FLOPS WITH GATE PRIMITIVES
The basic RS latch can be designed using gate primitives. Two instantiations of NAND or NOR gates suffice here. More involved flip-flops, registers, etc., can be built around these. Some of the level triggered versions of such flip-flops are taken up for design. Subsequently, the edge-triggered flip-flop of the 7474 type is developed in a skeletal form.
Example 5: A Simple Latch
Fig.24 shows the design description of a simple latch formed with two NAND gates.
Fig.24 A module to instantiate AND gate primitive and test it
A test bench for the same is shown in Fig.25 along with the results of the simulation run for 20 time steps. The test-bench has a block within a begin- end construct which reassigns values t or b and sb at two successive time step intervals. The whole sequence described within the block lasts for 10 ns. Defining the block within the always construct repeats the above assignment sequence cyclically until the simulation stops. The latch has been synthesized, and the synthesized circuit is shown in Fig.26.
Pending : Fig.25. A test bench for the flip-flop and its Simulation results
Pending : Fig.26 Synthesized circuit of the flip-flop module
Example 6: An RS Flip-Flop
The design module of an RS flip-flop along with a test bench for the same is shown in Fig.27. The module is a slight modification of the flip-flop of Fig.24. The simulation results are shown in Fig.28.
The synthesized circuit is shown in Fig.29. One can easily relate the difference between this circuit and that of Fig.26 to the corresponding difference between the respective design modules.
Pending : Fig.27 Module of an RS flip-flop with NAND gates and its test bench
Pending : Fig.28 Results of test bench for RS flip-flop
Pending : Fig.29 Synthesized circuit of the RS flip-flop module
Example 7: A Clocked RS Flip-Flop
The module in Fig.30 is for a clocked RS flip-flop. It is the RS flip-flop of Fig.27 with the clock signal gating the R and S inputs.
A test bench for the flip-flop is also shown in the figure. The clock waveform in the test bench is a square wave with a period of 4 ns. The simulation results are shown in Fig.31. Fig.32 shows the synthesized circuit of the flip-flop.
Pending : Fig.30 Module of a clocked RS flip-flop using NAND gates and its test bench
Pending : Fig.31 Results of test bench of clocked RS flip-flop
Pending : Fig.32 Synthesized circuit of the clocked RS flip-flop module
Example 8: A D-Latch
The design description of a D latch is given in Fig.33. It has one instantiation of the basic flip-flop of Fig.24. A test bench for the latch is also included in the figure. The simulation results are shown in Fig.34. Two versions of the synthesized circuit are shown in Fig.35 and Fig.36, respectively. The basic latch – which was instantiated in the module of Fig.33 — is shown as a black box in Fig.35. The internals of the latch are shown in Fig.36, which brings out the hierarchy clearly.
Pending : Fig.33 Module of D latch and its test bench
Pending : Fig.34 Results of the test bench for D latch
Pending : Fig.35 Synthesized circuit of the D latch module
Pending : Fig.36 Synthesized circuit of the D latch module showing hierarchy
DELAYS
Verilog has the facility to account for different types of propagation delays of circuit elements. Any connection can cause a delay due to the distributed nature of its resistance and capacitance. Due to the manufacturing tolerances, these can vary over a range in any given circuit. Similar delays are present in gates too. These manifest as propagation delays in the 0 to 1 transitions and 1 to 0 transitions from input to the output. Such propagation delays can differ for the two types of transitions. A variety of such delays can be accommodated in Verilog. Sometimes manufacturers adjust input and output impedances of circuit elements to specific levels and exploit them to reduce interface hardware. These too can be accommodated in Verilog design descriptions.
Net Delay
One of the simplest delays is that of a direct connection – a net. It can be part of the declaration statement
wire #2 nn; // nn is declared as a net with a propagation delay of 2 time steps
Here nn is declared as a net with an associated propagation delay of 2 time steps. The delay is the same for the positive as well as the negative transitions. The same is illustrated in Fig.44 (a), which connects two circuit blocks through a net nn with a delay of 2 time steps associated with it. The module in Fig.45 is a simple realization of the same. A test bench for the module is also shown in the figure. The simulation results are shown in Fig.44 (b), which brings out the effect of the net delay clearly.
Similar delays can be assigned to other types of nets as well. Whenever a variable or a signal is defined as a net and no delay is specified for it, the associated delay is taken as zero. This is true of instantiations of modules as well. The impedance connected as well as the type of loading can differ for the two transitions. The propagation delay too can differ accordingly. Two such delays can be specified as follows:
Wire #(2, 1)nm;
Here nm is declared as a net with two distinct propagation delays; the positive (0 to 1) transition has a delay of 2 time steps associated with it. The negative(1 to 0) transition has a delay of 1 time step. The delays are explained in Fig.46. The module of Fig.45 has been modified and shown in Fig.47; the propagation delays are different for rise and fall here.
Pending : Fig.44A net connecting two circuit blocks and the delay through it (a) Connection diagram (b) Input and output waveforms
Pending : Fig.45 A module to illustrate net delay and its test bench
Pending : Fig.46 A net connecting two circuit blocks and the delay through it (a) Connection diagram (b) Input and output waveforms
Pending : Fig.47 A module to demonstrate different delays for rise and fall times on net
Gate Delay
Gates too can have delays associated with them. These can be specified as part of the instantiation itself.
and #3 g ( a, b, c);
The above represents an AND gate description with a uniform delay of 3 ns for all transitions from input to output. A more detailed description can be as follows:
and #(2, 1) (a, b, c);
With the above statement the positive (0 to 1) transition at the output has a delay of 2 time steps while the negative (1 to 0) transition has a delay of 1 time step. Fig.48 shows a module to illustrate the delays associated with gate primitives. A test bench for the same is also shown in the figure. The results of running the test bench are shown in Fig.50. The AND gate instantiation in Fig.48 has different delays for the output transitions; respective waveforms are shown in Fig.49.
Pending : Fig.48 Module to demonstrate the delays using gates
Pending : Fig.49 AND gate instantiations with different delays for the positive and negative transitions
(a) Gate instantiated (b) Associated waveforms
Pending : Fig.50 Results of test bench
In a more detailed design description, delays can be associated with nets as well as gates. Consider the design description shown in Fig.51 (a). It has a total of 8 different time delay values specified. All these are hypothetical and different from each other. It is done intentionally to bring out the effect of each of them on the concerned gates and signals. The circuit for this design description is shown in Fig.51 (b). Typical waveforms of input signals as well as other signals are shown in Fig.52, to illustrate the different delays in the design description.
Fig.52 (a) and Fig.52 (b) illustrate how changes in one of the inputs – b1 – affect the other signals; the signals and gates affected are shown highlighted in Fig.52 (a). Throughout this period, input c1 is taken as at 1 state while inputs b2 and c2 remain at 0 state. The propagation delays of signals at point P and Q and that for the signal a are shown in Fig.52(b). These conform to the delays specified in the design segment of Fig.51 (a). Subsequently, input c1 goes down to 0 state and input b1 remains at 0 state itself. Only signal b2 changes. The affected signals and gates are shown highlighted in Fig.52 (c). The waveforms of signals affected and the associated propagation designs are shown in Fig.52 (d). These too conform to the program segment of Fig.51 (a).
Pending : Fig.51 (a) A design having eight different time delay values
Pending : Fig.51 (b) The circuit for the above module
Pending : Fig.52 Illustration of signal delays in the design description segment in Fig.51
(a) The circuit portion active during changes to signal b1
(b) Signal waveforms following changes to signal bl
(c) The circuit portion active during changes to signal b2
(d) Signal waveforms following changes to signal b2
Delays with Tri-state Gates
For tri-state gates the delays associated with the control signals can be different from those of the input as well as the output. The instantiation inclusive of this is shown in Fig.53 for a tri-state buffer of the bufif1 type. Three time delay values are specified:
1. The first number represents the delay associated with the positive (0 to 1)transition of the output.
2. The second number represents the delay associated with the negative (1 to 0)transition of the output.
3. The third number represents the delay for the output to go to the hi-Z state as the control signal changes from 1 to 0 (i.e., ON to OFF command).
Pending : Fig.53 Delays associated with typical tri-state gate
Delays for the other tri-state buffers – namely bufif0, notif1 and notif0 – may be specified in a similar manner.
The turn-off time — 2 time steps here — represents the time for which the charge will be stored in the output line after the control line turns off. Values of delay time and storage time can be specified in this manner for all the types of tri- state type gates. The following are noteworthy here:
• Delays and storage times can be specified on the gate primitives and the nets but not on regs.
• All three time values are separately specified in the most versatile case.
• If only two time-values are specified, these are interpreted by Verilog as the rise (0 to 1) and fall (1 to 0) time, respectively. The turn-off time (delay) is taken as the smaller of these two.
• If only one time value is specified, it is taken as the rise time, the fall time, and the turnoff time.
• If no time value is specified, the rise and fall times at the output are taken as zero. The turn-off is taken as instantaneous.
Normally the delay time of any IC varies over a range for ICs from different production batches (as well as in any one batch). It is customary for manufacturers to specify delays and their range in the following manner:
• Max delay: The maximum value of the delay in a batch; that is, the delay encountered in practice is guaranteed to be less than this in the worst case.
• Min. delay: Minimum value of delay in a batch; that is, the specified signal is guaranteed to be available only after a minimum of time specified.
• Typ. Delay: Typical or representative value of the delay.
Each of the delays in a gate primitive or for a net can be specified in terms of these three values. For example
and #(2:3:4) g1(a0, a1, a2);
can instantiate an AND gate with the following time delay specifications:
• The 0 to 1 rise time and the 1 to 0 fall time are equal.
• The minimum value of either is 2 time steps. Typical value is 3 time steps and the maximum value is 4 time steps.
• Note that the colon that separates the numbers signifies that the timings specified are the minimum, typical, and maximum values. At the time of simulation, one can specify the simulation to be carried out with any of these three delay values. If the same is not specified, the simulation is carried out with the typical delay value.
The group of minimum, typical, and maximum delay values for the propagation delays can be specified separately for any gate primitive. Thus an AND gate primitive can be specified as and #(1:2:3, 2:4:6) g2(b0, b1, b2);
Here for the 0 to 1 transition of the output (rise time) the gate has a minimum delay value of 1 ns, a typical value of 2 ns, and a maximum value of 3 ns. Similarly, for the 1 to 0 transition (fall time) the gate has a minimum delay value of 2 ns, a typical delay value of 4 ns, and a maximum delay value of 6 ns. Such delay specifications can be associated with nets as well as tri-state type gates also.
Examples
wire #( 1:2:3) a; /1 The net a has a propagation delay whose minimum, typical and maximum values are 1 ns, 2 ns, and 3 ns, respectively*/
buf if 1 #(1:2:3, 2:4:6, 3:6:9) g3 (aO, bO, cO);
/* The different delay values for the buffer are as follows:
• The output rise time (0 to 1 transition) has a minimum value of 1 ns, a typical value of 2 ns and a maximum value of 3 ns.
• The output fall time (1 to 0 transition) has a minimum value of 2 ns, a typical value of 4 ns and a maximum value of 6 ns.
• The output turn-off time (1 to 0) has a minimum value of 3 ns, a typical value of 6 ns, and a maximum value of 9 ns. */
• A typical design can have a number of circuit blocks like gates, flip-flops, etc., with associated interconnections. The individual nets and gates may have their own separate delays. The following general observations are in order regarding the overall delays through the circuit: The cumulative delay for a signal in a path puts an upper limit on the maximum operating frequency vis-a-vis the signal.
• A signal may go through multiple paths in a design to arrive at one gate. It is necessary to match the delays within specified tolerances for reliable operation of the device.
• In larger designs, one has to identify the longest signal path (critical path). This puts an upper limit on the operating frequency apart from causing mal- operation in a worst-case scenario. One of the practices in design is to reroute selected signals or redo selected design segments to reduce critical path delays.
STRENGTHS AND CONTENTION RESOLUTION
In practical situations, outputs of logic gates and signals on nets in a circuit have associated source impedances. When the outputs of two gates are joined together, the signal level is decided by the relative magnitudes of the source impedances. Sometimes a disparity between the impedances is intentionally introduced to minimize circuit hardware. Effects of such differences in the impedances are indirectly introduced in design descriptions by assigning “strengths” to specific signals. Signal strength declarations are of two types – those associated with outputs of gate primitives and those with nets
Strengths of Gate Primitives
Gate output strengths can be specified separately. Table 5 gives the names associated with strengths, respective abbreviations, and their order by weight. These hold good for logic 1 state as well as the 0 state.
Pending : Table 5 Strength levels associated with outputs of gate primitives
The strengths associated with the output of a gate primitive can be specified separately for the two logic levels. The format for the same is shown in Fig.54 for a specific case; the format remains the same for all types of gate primitives.
Pending : Fig.54 Format for specifying strengths in the instantiation of a gate primitive
Strength Contention in Gate Primitives
When two signals of opposite polarity and differing strengths drive a line, the output status is decided by the stronger signal. However, if the signals are of equal strength, the output is indeterminate. Different contention possibilities arise here. The variety is brought out through examples.
Example 10: Strength Contention
Consider the module in Fig.55. The logic levels taken by the signal O for different combinations of inputs to the two buffers g1 and g2 are shown in Table 6. Contentions of signals with other combinations of levels can be resolved in the same manner
Pending : Table 6 Outputs for different inputs for the example of Fig.55
Pending : Fig.55 (a) A module to illustrate strength contention
The outputs for the four input combinations are given in the table. Whenever there is a contention, the logic value of the output is decided by the stronger signal. In fact the design description here realizes an OR gate at the output side without additional hardware. It does not lead to any ambiguity.
Pending : Fig.55 (b) Output of module in Fig.55 (a)
Consider the Example in Fig.56, which is a slightly modified version of that in Fig.55. The output logic values for different input combinations are given in Table 7. The gate outputs are decided by following the same logic as in the last case. However, in one case — when both gates “drag” the output with equal strength in opposite directions — the output logic level is indeterminate — that is, x.
Pending : Fig.56 Illustration of strength contention resulting in x-type output and simulation results
Pending : Table 7 Outputs for different inputs in the example of Fig.56
Net Charges
Whenever a net is driven by a signal, it takes the logic value of the signal. When the signal source is tri-stated, the net too gets tri-stated. In practice the net can have a capacitor associated with it, which can store the signal level even after the signal source dries up (i.e., tri-stated). To account for this situation, a charge storage capacity is associated with the net. Such nets are declared with the keyword trireg. By virtue of the inherent capacitance associated with them, trireg nets can never be in the high impedance state – that is, they can assume 0, 1, or x value only. A trireg net can be in one of two possible states only:
Driven state: When driven by a source or multiple sources, the net assumes the strength of the source. It can be any of the strengths specified in Table 5.1 except the high impedance value.
Capacitive state: When the driven source (sources) is (are) tri-stated, the net retains the last value it was in – by virtue of the capacitance associated with it. The value can be 0, 1 or x (but not the high impedance value).
When in the capacitive state, a net can have a storage strength associated with it. Three such storage strengths are possible – namely large, medium, and small. Their details are shown in Table 8. When a storage strength is not specified, it is assigned the default value -medium. For a trireg net one cannot assign storage strength capacity separately for the 0 and the 1 states.
Pending : Table 8 Capacitive storage strengths on nets
Example 11: Net Storage
Consider the design in Fig.57. As long as the signal control = 1, the signal out follows the signal in. When control goes to 0, out is disconnected from the input and it “floats.” It retains the last value due to the capacitance storage capacity. The storage strength is medium, signifying a medium value of capacitance.
Pending : Fig.57 Illustration of net storage and simulation results
Contention Between Net and Gate Primitive Outputs
In case of a contention between a signal output from a gate and the charge on a net, the contention is decided by the relative strengths of the signals on each. Table 9 combines all the strengths – those of the gate outputs as well as those of tri-stated nets and — lists them in the order of their relative strengths.
Pending : Table 9 Signal strength names and their relative weights
Net Types and Port Assignments
All input ports of modules have to accept inputs from outside when instantiated and respond to changes in them. Hence they have to be of net type. Note that input ports cannot be of reg type since their values cannot be changed from outside. The output ports of instantiated modules can be of net or reg types. Inout ports have to function as input or output ports; hence they too have to be of net types.
The port assignments in an instantiation can be to scalars, vectors, part vectors, or concatenated vectors. However, their sizes should match those of the ports in the module definitions. Further, the type restrictions mentioned above have to be complied with. In many situations the net types in the module definition and its instantiation may differ in the case of input and inout ports. In such cases the resulting net type can be of only one type. Either the net type declared in the module definition or that in the instantiation (external type) dominates. The choice is decided by a specific protocol in the LRM. Table 10 gives details. As can be seen from the table, whenever the two net types lead to a logical clash, the external data type prevails.
Pending : Table 10 Net assignments with port connections
NET TYPES
Wire is possibly the simplest type of net declaration, trireg considered in the last section is another. A variety of other net types are possible. Most of them are provided for specific types of contention resolution.
wand and wor Types of Nets
Strengths on nets can be decided in ways other than a direct declaration also. These offer additional flexibility to the circuit designer. Consider the example of Fig.56 for which the input-output values are shown in Table 7. For the signal input combination i1 = 0 and i2 = 1, signal O is indeterminate. However, it may be made specific in two alternate ways: ‘wand’ and wor are two types of net declarations for such contention resolution, wand is a wire declaration, which resolves to AND logic in case of contention, wor is a wire declaration, which resolves to OR logic in case of a contention.
Example 12: Illustration of wand type net
Fig.58 shows a design module where the outputs of two buffers drive the same net; the net has been declared to be a wand type, and any contention with the possibility of indeterminate output is resolved according to AND logic. A test bench and simulation results are also shown in the figure. The input and output logic values and the nature of contention resolutions wherever it occurs are listed out in Table 11 also. Contention can be seen to be resolved in two possible ways:
• When i1 = 1 and i2 = 0, the stronger signal i 1 at the 1 level prevails and o = 1. The contention is resolved according to the strengths.
• When i1 = 0 and i2 = 1, both signals being equally strong, the value of o is decided according to AND logic.
The synthesized version of the circuit is shown in Fig.59; the circuit translates into an AND gate which is erroneous.
Pending : Fig.58 Illustration of use of the wand-type net and simulation results
Pending : Table 11 Output values for different inputs of the design in Fig.58
Pending : Fig.59 Synthesized version of the module with the wand-type net
Example 13: Illustration of wor-type net
Consider the design segment in Fig.58 with o being declared as a wor type of net instead of a wand type. The corresponding design module is shown in Fig.60. A test bench and simulation results are also shown in the figure. The outputs for all possible combinations of inputs are given in Table 12. Contention can be seen to be resolved in two possible ways:
• When il = 1 and i2 = 0, the stronger signal il at the 1 level prevails and o = 1. The contention is resolved according to the strengths.
• When il = 0 and i2 = 1, both signals being equally strong, the value of o is decided according to OR logic.
The synthesized version of the circuit is shown in Fig.61; the circuit translates into an OR gate; this is consistent with the desired input-output relationship shown in Table 12.
Pending : Fig. 60 Illustration of use of the wor-type net and simulation results
Pending : Table 12 Output values for different inputs of the design in Fig.60
Pending : Fig.59 Synthesized version of the module with the wor-type net
Observations:
• Many synthesizers do not support wired-or logic, wand and wor may be used to advantage when supported by the synthesizer.
• The net triand is functionally identical to the net wireand. Similarly, the net trior is functionally identical to the net wireor.
• All synthesizers support wire. Triand, trior, triO, and tril (discussed below) may not be supported by some.
11.2 Tri
The keyword tri has a function identical to that of wire. When a net is driven by more than one tri-state gate, it is declared as tri rather than as wire. The distinction is for better clarity. Similarly, triand and trior are the counterparts of wand and wor, respectively.
Example 14: Illustration of tri-type net
Consider the design segment in Fig.62. Here the signal on net out is controlled by the control signal En. If En = 1, signal a is steered to the net out and the output of gate g2 is tri-stated. On the other hand, if En = 0, signal b is steered to the net out and the gate g1 is tri-stated. If the buffers are controlled by independent Enable signals, the output is resolved according to the respective strengths.
Pending : Fig.62 A segment of a design to illustrate tri type of net
11.3 Tri0 and tri1
If the output of a tri-state buffer is to be pulled up to the 1 state when tri-stated, it is declared as net tri1. Similarly, it is declared as tri0 if it is to be pulled down to 0 state when tri-stated. Tri0 and tri1 provide respective default outputs and avoid any following circuit having a tri-stated input. In turn, it may manifest as an added load at the concerned gate output. The example in Fig.63, which shows a design segment, illustrates an application. Table 13 lists the output values of signals considered in the design segment of Fig.63. Referring to the figure (and the table), one can see that when En = 0, all three buffers g0, g1, and g2 are off. Net o3, being a wire is tri-stated and is in z state. However, net o1,
being of tri0 type, is pulled down to 0 state irrespective of the input value. Net 02, being of tri1 type, is pulled up to 1 state. When En = 1, all three buffers are ON and the respective outputs follow the input. Thus though g0, g 1, and g2 are functionally identical, they behave differently due to the difference in the type of the respective output nets.
Reset, Chip Enable and similar signals can be pulled up or down as required with tri0 or tri1; this signifies the normal status -that is, the chip is disabled or the reset is disabled. As and when the chip is to be enabled, the same is done by enabling the buffer for the required period. Similarly, the reset can be activated for a specified period to reset the chip; subsequently, the reset can be deactivated to restore normal operation of the chip.
Pending : Fig. 63 A segment of a design to illustrate tri0 and tri1 types of net
Pending : Table 13 Output values for different inputs of the segment in Fig.63
11.4 supply0 and supply1
Supply0 and supply1 are the keywords signifying the high- and low-side supplies. Nets to be connected to the Vcc supply are declared as supply1, and those to be grounded are declared as supply0.
11.5 Ambiguous Strengths
Certain x or z type of input port values of gate primitives can lead to outputs of apparently ambiguous strengths. A number of such situations can arise. Such cases are brought out and illustrated in the LRM. Nevertheless, such ambiguous situations may be avoided in practice.
11.6 Combining Delays & Strengths
One can combine delays and strengths in net declarations as well as in instantiation of gate primitives. The formats for the same are illustrated below
Wire (drive_strength_1, drive_strength_0) # (delay_0_1, delay_1_0,turn_off_delay)
signal1, signal2;
Gate type (drive_strength_1, drive_strength_0) # (delay_0_1, delay_1_0, turn_off_delay) instance_1(signal1, signal2);
For each of the delays above, one can also specify the minimum, typical, and maximum values. Such values can be specified in terms of constant expressions also.
DESIGN OF BASIC CIRCUITS
Elementary gates are the basic building blocks of all digital circuits – whether combinational, sequential, or involved versions combining both. Conversely, any digital circuit can be split up into constituent elementary gates. Any digital circuit however involved it may be, can be realized in terms of gate primitives. The step-by-step procedure to be adopted may be summarized as follows:
1. Draw the circuit in terms of the gates.
2. Name gates and signals.
3. Using the same nomenclature as above, do the design description.
4. As the functional blocks like encoder, decoder, half-adder, full-adder, etc., get more and more involved, treat each as a building block with corresponding inputs and outputs.
5. Make more involved circuits in terms of the building blocks — as far as possible. Each block within another block manifests as an instantiation of one module within another
Example 15: ALU
We consider the design of an ALU as an example of a relatively complex design. The ALU considered carries out four functions:
• Addition of two 4-bit numbers.
• Complementing all the bits of a 4-bit vector.
• Bit-by-bit AND operation on two nibbles.
• Bit-by-bit XOR operation on two nibbles.
Pending : Fig.64 a 4-bit adder module and its test bench
A set of 2 mode select bits selects the function to be carried out from amongst the above four. The design has been evolved in a step-by-step manner. Fig.64 shows a 4-bit adder module and a test-bench for it. The simulation results are given in Fig.65. The adder module is built up by repeated instantiation of the full-adder module. The synthesized version of the adder is shown in Fig.66. The full-adder module instantiations appear here as black boxes with respective inputs and outputs.
Pending : Fig.65 Simulation results of Fig.64
Pending : Fig.66 Synthesized circuit of the adder module
Fig.67 shows a module to AND two nibbles. It is done through direct instantiation of AND gate primitives for two inputs. The corresponding synthesized circuit is shown in Fig.68
Pending : Fig.67 A 4-bit Adder Module
Pending : Fig.68 Synthesized circuit of the andg4 module
The module in Fig.69 carries out the bit-wise XOR operation on 2 nibbles. Its synthesized circuit is shown in Fig.70. Similarly, the module in Fig.71 complements 2 nibbles in a bit-wise manner. The corresponding synthesized circuit is shown in Fig.72
Pending : Fig.69 A 4-bit XOR module
Pending : Fig.70 Synthesized circuit of the XOR module
Pending : Fig.71 A module to complement a 4-bit vector
Pending : Fig.72 Synthesized circuit of the module in Fig.71
A 2-bit binary number with its 4 distinct states can be used to select any one of the 4 desired functions; it calls for the use of a 2-to-4 decoder. Such a module is shown in Fig.73, and its synthesized circuit is shown in Fig.74.
Pending : Fig.73 A 2-to-4 decoder module
Pending : Fig.74 Synthesized circuit of the decoder module
As explained above, the decoder outputs can be used to select anyone of the 4 functional outputs and steer it to the final output; a 4-to-l mux serves this purpose. The mux module is shown in Fig.75; its synthesized circuit is in Fig.76.
Pending : Fig.75 A 4-to-1 mux module
Pending : Fig.76 Synthesized circuit of the mux module
The overall ALU module is shown in Fig.77. It instantiates all the above modules. Depending on the mode specified, one of the four functions is selected by the 2-to-4 decoder; its output is multiplexed on to the output by the 4-to-l mux. The ALU module here has been synthesized and shown in Fig.78. Each functional block instantiated in Fig.77 appears here as a corresponding distinct black box.
More functions can be added, if desired, to make the ALU more comprehensive. The ALU size can be increased to 16 or 32 bits by repeated instantiation of the 4-bit module in a more comprehensive module
Pending : Fig.77 A 4-bit ALU module
Pending : Fig.78 Synthesized circuit of the ALU module
MODELING AT DATAFLOW LEVEL
INTRODUCTION
Gate level design description makes use of the gate primitives available in Verilog. These are repeatedly and judiciously instantiated to achieve the full design description. Digital designers familiar with the basic logic gates and SSI / MSI circuits can describe the desired target circuit in terms of them on paper and proceed with the design description based on them. It is practical for comparatively smaller designs – say those involving tens of gates.
One can define modules in terms of primitives involving tens of gates and instantiate them in
macro-modules. This increases the complexity of designs that can be handled by one order. Beyond that the gate level design description becomes too complicated to be practical. Data flow level description of a digital circuit is at a higher level. It makes the circuit description more compact as compared to design through gate primitives. We have a number of operands and operations representing the simulations directly or indirectly. The operations are carried out on the operand(s) in singles or in combinations. The results are assigned to nets. The operand- operation-assignments representing data flow are carried out repeatedly to complete the design description. Further, these can be combined judiciously with the gate instantiations wherever necessary. With such combinations, design description of a comprehensive nature can be accommodated.
CONTINUOUS ASSIGNMENT STRUCTURES
A simple two input AND gate in data flow format has the form
assign C = a && b;
Here “assign” is the keyword carrying out the assignment operation. This type of assignment is called a continuous assignment.
• a and b are operands – typically single-bit logic variables.
• “&&” is a logic operator. It does the bit-wise AND operation on the two operands a and b.
• “=” is an assignment activity carried out.
• C is a net representing the signal which is the result of the assignment. In general, an operand can be of any one of the following types:
• A constant number [including real].
• Net of a scalar or vector type including part of a vector.
• Register variable of a scalar or vector type including part of a vector.
• Memory element.
• A call to a function that returns any of the above. The function itself can be a user-defined or of a system type.
There are other types of operators as well. All types of combinational circuits can be modeled using continuous assignments. One need not necessarily resort to instantiation of gate primitives.
An AND gate module which uses the above assignment is shown in Fig.79. The test bench for the same is shown in Fig.80, and the waveforms of nets a, b, and c obtained with the simulation are shown in Fig.81. The simulation software used has the facility to capture the waveforms of selected signals in the “ran” phase; this has been invoked to get the waveforms in Figure 6.3. No separate $monitor command is included in the test bench of Fig.80.
Pending : Fig.79 A module with an AND gate at the data flow level
Pending : Fig.80 Test bench of Fig.79
Pending : Fig.81 Input and Output Waveforms
Multiple assignments can be carried out through a direct extension of the structure adopted in the above case. Consider the AOI gate in Fig.82. A few patterns of the assignments for the circuit are given in Fig.83 to Fig.84. Multiple assignments can be carried out through a direct extension of the structure adopted in the above case. Consider the AOI gate in Fig.82. A few patterns of the
assignments for the circuit are given in Fig.83 to Fig.85.
Pending : Fig.82 An A-O-I Gate
Pending : Fig.83 Data flow level assignment statements for A-O-I gate
Pending : Fig.84 Another set of data flow level assignments for A-O-I gate
Pending : Fig.85 Another set of data flow level assignment for A-O-I gate
Observations:
• The semicolon terminates an assignment statement. Commas separate different assignments in an assignment statement.
• “|” is the bit-wise OR operator and the bit-wise negation operator in Verilog.
• All the quantities in the left-hand side of a continuous assignment have to be of net type. Thus e, f, g, and gl have to be declared as nets.
• All the operations in an assignment are evaluated whenever any of the operands in the assignment changes value. Further, all the assignments are carried out concurrently. Hence the order of the assignments or the statements is immaterial.
• The right-hand sides of assignment statements can be nets, legs, or function calls. Here a, b, c, and d can be nets or legs. All other variables have to be nets. The module for the A-O-I gate of Fig.79 is given in Fig.86 – it is formed around the assignment statement of Fig.83. The same can be tested through a test bench.
Combining Assignment and Net Declarations
The assignment statement can be combined with the net declaration itself making the assignment implicit in the net declaration itself. Thus the two statements
wire C;
assign C = a & b;
Can be combined as wire C = a & b;
The above simplification cannot be carried over to multiple declarations. With this proviso, the module of Fig.86 can be modified as shown in Fig.87. In the modules of Fig.86 and Fig.87, a, b, c, and d are declared as input and g as output. These would be taken as nets if there are no separate declarations concerning their types. However, the intermediate quantities – e, f, and g1— should be declared as wire. Synthesized version of the A-O-I circuit is shown in Fig.88.
Pending : Fig.86 A compact description of the AOI module at the data flow level
Pending : Fig.87 Alternate design module to realize the A-O-I gate
Pending : Fig.88 Synthesized circuit of the A-O-I gate module
Continuous Assignments and Strengths
A net to which a continuous assignment is being made can be assigned strengths for its logic levels. The procedure is akin to the strength allocation to the outputs of primitives. The AOI gate of Fig.87 is modified with strength allocations to the output and is shown in Fig.89. The assignment to g can be combined with the wire declaration into a single statement as
wire (pulll, strongO)g = ~g1;
As mentioned earlier, one can have only one assignment in the statement here. In a bigger design, g in Fig.89 can be assigned to other expressions or primitives also.
Pending : Fig.89 The A-O-I gate with strength allocation
DELAYS AND CONTINUOUS ASSIGNMENTS
Delays can be incorporated at the data flow level in different ways. Consider the combination of statements in Fig.90. The assignment takes effect with a time delay of 2 time steps. If a or b changes in value, the program waits for 2 time steps, computes the value of c based on the values of a and b at the time of computation, and assigns it to c. In the interim period, a or b may change further, but c changes and takes the new value only 2 time steps after the change in a or b initiates it. Typical waveforms for a, b, and c are shown in Fig.91. Note that the changes in a and b of duration less than 2 time steps are ignored vis-a-vis assignment to the net c. The following may be noted with respect to the waveforms:
a changes at 0 ns, 2 ns, 5 ns, 8 ns, 9 ns, 12 ns and 13 ns; b changes at 0 ns, 2 ns, 6 ns, 8 ns and 13 ns. All these trigger changes toc.
In every case change to C comes into effect with a time delay of 2 time steps – that is, at the 2nd, 4th, 7th, 8th, 10th, 11th, 14th and 15th ns, respectively.
Whenever C changes, its new value is decided by the values of a and b at that instant of time. In effect, c changes at 2nd, 4th and 7th ns only.
Pending : Fig.90 Delays with assignments
The program segment in Fig.91 also gives the same output as shown in Fig.92.
Pending : Fig.91 Alternate design description for delays with assignments
Pending : Fig.92 Input and Output Waveforms
If the time delay is in the net and not in the assignment proper, its effect is not any different. Consider the program segment in Fig.93. Here the changes in the values of d are computed immediately following those in a and b. The assignment takes effect immediately. The delay in the net C causes a delay of 2 time steps in the assignment to C. Such a delay is not present for d. Typical waveforms for the program segment are shown in Fig.94. Note the following:
• a changes at 2 ns, 5 ns, 8 ns, 9 ns, 12 ns and 13 ns; b changes at 2 ns, 6 ns, 8 ns and 13 ns. All these trigger changes to C and d also.
• In every case, change to C comes into effect with a time delay of 2 time steps – that is, in effect, c changes at 2nd, 4th and 7th ns only.
• Whenever C changes, its new value is decided by the values of a and b at that instant of time.
• In every case, changes to d come into effect immediately
Pending : Fig.93 Combining delays with assignments
Pending : Fig.94 Input and output waveforms
ASSIGNMENT TO VECTORS
The continuous assignments are equally applicable to vectors. A single statement can describe operations involving vectors wherever possible. This is illustrated in the adder module in Fig.95, which adds two 8-bit numbers. Here it is assumed that the sum is also of 8 bits. However to account for the possibility of a carry bit being generated in the course of the addition process, it is desirable to increase the vector size of c by one bit.
Pending : Fig.95 An Adder module at data flow level
Concatenation of Vectors
One can concatenate vectors, scalars, and part vectors to form other vectors. The concatenated vector is enclosed within braces. Commas separate the components -scalars, vectors, and part vectors. If a and b are 8- and 4-bit wide vectors, respectively and c is a scalar {a, b, c] stands for a concatenated vector of 13 bits width. The vector components are formed in the order shown – c is the least significant bit and a[7] the most significant bit and the other bits are in between in the order specified. The concatenation can be with selected segments of vectors also. For example, {a(7:4), b(2:0)} represents a 7-bit vector formed by combining the 4 most significant bits of vector a with the 3 least significant bits of vector b. The size of each operand within the braces has to be
specified fully to form the concatenated vector. Hence unsized constant numbers cannot be used as operands here.
Example 16: Eight-Bit Adder
Fig.96 shows the design description of an 8-bit adder, where the output vector is formed directly by concatenation. The adder takes a carry input and gives out a carry output. The adder module here can form the “seed” adder block in a multi- byte adder chain.
Pending : Fig.96 A complete 8-bit adder module at data flow level
When it is necessary to replicate vectors, scalars, etc., to form other vectors, the same can be arrived at in a compact manner using the repetition multiplier again through concatenation. Thus,
{2{p}} represents the concatenated vector {P, P}
{2{p}, q} represents the concatenated vector {p, p, q}
The two statements
assign GND=supply0;
p={8{GND}};
together ground the 8 bits of the vector p. Concatenation operation can be nested to form bigger vectors when component combinations are repeated. For example,
{a, 3 {2{b , c}, d}}
is equivalent to the vector
{a, b, c, b, c, d, b, c, b, c, d, b, c, b, c, d }
OPERATORS
A set of operators is available in Verilog. The operator symbols are similar to those in C language. With these operators we can carry out specified operations on the operands and assign the results to a net or a vector set of nets as the case may be.
Unary Operators
Unary operators do an operation on a single operand and assign the result to the specified net. The unary operators in Verilog are given in Table 6.1. All unary operators get precedence over binary and ternary operators. The operators “+” and preceding an integer or a real number change its sign. These are also unary operators, though not separately listed in Table 14.
Pending : Table 14 Unary Operators and their Symbols
Binary Operators
Most operators available are of the binary type. A binary operator takes on two operands; the operator comes in between the two operands in the assignment. The following are to be noted:
The arithmetic operators treat both the operands as numbers and return the result as a number.
All net and reg operand values are treated as unsigned numbers.
Real and integer operands may be signed quantities.
If either of the operand values has a zero value, the entire result has a zero value (?).
The result of any arithmetic operation — with the “+” or ” or with any of the other arithmetic operators will have an x value if any of the operand bits has an x or a z value.
Arithmetic Operators
The arithmetic operators of the binary type are given in Table 15. The modulus operand is similar to that in C language – It provides the remainder of the division of two numbers. The module in Fig.95 is an example of the illustration of the use of the arithmetic binary operator “+” (for addition). Other arithmetic operators are also used in a similar manner.
Pending : Table15 Arithmetic Operators and their Symbols
Observations:
In integer division the fractional part of the result is truncated and ignored.
If any bit of an operand is x or z in an arithmetic operation, the result takes the x value.
If the first operand of a modulus operator is negative, the result is also a negative number. Depending on the type of definition of a number, a modulus operation can lead to different results. Typical examples are given in Table 16.
Pending : Table 16 Typical modulus operations and their results
Logical Operators
There are two logical operators involving two operands. The operands concerned can be variables or expressions involving variables. In both cases the result of the operation is a single bit of value 1 (true) or 0 (false). If a bit in one of the operands is x or z, the result of evaluation of the expression has an x value. The operator details are shown in Table 17. The modules in Fig.86 and Fig.87 are examples of the illustration of the use of logical binary operators.
Pending : Table 17 Binary Logical Operators and their Symbols
Relational Operators
There are four relational operators; their details are shown in Table 18. A relational operator treats both the operands as binary numbers and compares them. The result is a 1 (true) bit or a 0 (false) bit. If a bit in either operand is x or z, the result has x (unknown) value. The operands can be variables or expressions involving variables. Operands of net or reg type are treated as unsigned numbers. Real and integers can be positive or negative (i.e., signed) numbers.
Pending : Table 18 Relational Operators and their Symbols
Equality Operators
The equality operator makes a bit-by-bit comparison of the two operands and produces a result bit. The result bit is a 1 (true) if the operand condition is satisfied; otherwise it is 0 (false). The operands can be variables or expressions involving variables. If the operands are of unequal length, the shorter one is zero filled to match the larger operand. The operators in this category are only of two types – those to test the equality and those to test inequality. The four operators in this category are given in Table 19.
Pending : Table 19 Equality Operators and their Symbols
Bit-wise Logical Operators
The operator does a specified bit-by-bit operation on the two operands and produces a set of result bits. The result is (bit-wise) as wide as the wider operand. If the width of one of the operands is less than that of the other, it is bit-extended by filling zero bits and the widths are matched. Subsequently, the specified operation is carried out. If one of the operands has an x or z bit in it, the corresponding result bit is x. Either operand can be a single variable or an expression involving variables. Table 20 gives the four operators of this category.
Pending : Table 20 Logical Operators and their Symbols
Operator Truth Table
The truth tables for different types of bit-wise operators are given in Table 21. Note that an z input is treated as an x value.
Pending : Table 21 Truth Tables for Bit-wise Operators
Shift Operators
Table 22 shows the two operators of this category. The « operator executes left shift operation, while the » operator executes the right shift operation. In either case the operand specified on the left is shifted by the number of bits specified on the right. The shifting is done irrespective of whether the bits are 0, 1, x, or z. The bits shifted out are lost. The vacated positions created as a result of the shifting are filled with zeroes. If the right operand is x or z, the result has an x value. If the right operand is negative, the left operand remains unchanged.
Pending : Table 22 Shift type Operators and their Symbols
Ternary Operator
Verilog has only one ternary operator – the conditional operator. It checks a condition and does a branching. It is a versatile and powerful operator. It enhances the potential of design description substantially. The general form is
A?b:c
The conditional operation is made up of two operators – “?” and – and three operands. The two operands separate the three operators in the order shown. The operational sequence of the operation is as follows:
“A” is evaluated first.
If A is true, b is evaluated.
If A is false, c is evaluated.
If A evaluates to an ambiguous result, both b and C are evaluated. Then they are combined on a bit-by-bit basis to form the resultant bit stream. The result bit can have the following three possible values:
0 if the corresponding bits of b and c are 0.
1 if the corresponding bits of b and c are 1.
X otherwise.
As an example, consider the assignment statement
assign y = W ? X : z;
where W, X, y and Z are binary bits. If the bit W is true (1), y is assigned the value of X: otherwise – that is, if W is false (0) – y is assigned the value of Z. The assignment statement here multiplexes X and Z onto y; W is the control signal here. Consider the assignment
assign flag = (adrl ==adr2)?1’b1 : 1’b0;
Here adrl and adr2 are two multibit vectors representing two addresses. If the two are identical, the flag bit is set to zero; else it is reset.
assign zero_flag = (|byte)? 0:1;
All the bits of the byte are ORed together here. The zero_flag is set if the result is zero.
assign C = S ? a: b;
The net C is connected to a if S=1; else it is connected to b
The statement realizes a 2 to 1 mux. b and C have to be scalars or vectors of the same width. The assignment can be expanded to realize larger muxes. The conditional operator can be nested. Nesting gives rise to a variety of uses of the operator.
Pending : Fig.97 Illustration of nested conditional operations
As an example, consider the formation of an ALU. ALU can be defined in a compact
manner using the ternary operator.
assign d = (f==add)?(a+b): ((f==subtract)?(a-b): ((f==compl)?~a: ~b));
In the example here, f is taken as a control word. If it is equal to the number add, d is to be equal to the sum of a and b. If f is equal to the number subtract, d is to be equal to the difference between a and b. If it is equal to the number compl, d is to be the complement of a. Otherwise (i.e., f = 3) d is taken as the complement of b.
Operator Priority
A clear understanding of the operator precedence makes room for a compact design description. But it may lead to ambiguity and to inadvertent errors. Whenever one is not sure of the operator priorities, it is better to resort to the use of parentheses and ensure clarity and accuracy of expressions. Further, some synthesizers may not interpret the operator precedence properly. These too call for the apt use of parentheses. The operators are arranged in tabular form and shown in Table 23. The table brings out the order of precedence. The order of precedence decides the priority for sequence of execution and circuit realization in any assignment statement. The following form the basic rules for the same:
• Unary operators have the highest priority and execute first.
• Subsequently the binary operators execute. Amongst these the algebraic operators have the highest precedence. Amongst the algebraic operators *, / and % have precedence over + and – operators.
• Subsequent precedence amongst the binary operators is as shown in the table.
• Conditional operator has the lowest precedence and hence is executed last.
• In any expression, operators associate from left to right. Ternary operator is the only exception to this; it associates from right to left.
Pending : Table 23 Operator Precedence Details
BCD Adder
Pending : Fig.98 BCD Adder Module at the Data flow module
A BCD adder can be formed through a compact assignment using a ternary operator. The assignment statement has the form
assign {co, sumd} = (sumb<=4’b1001 )?{1 ‘b0,sumb}: (sumb + 4’b0110;
The adder module using the above assignment and a test-bench for the same are shown in Fig.98. The synthesized version of the circuit is shown in Fig.99. The results of running the test bench are given in Fig.100.
Pending : Fig.99 Synthesized circuit of the BCD Adder
Pending : Fig.100 Results of BCD Adder Module