UNIT V(Part II)

TYPES OF PROGRAMMABLE LOGIC DEVICES (PLD):

Programmable Arrays

• OR Array
• AND Array

Classifications of Simple Programmable Logic Devices (SPLD)

• Read-Only Memory (ROM)
• Programmable Array Logic (PAL)
• Programmable Logic Array (PLA)
• Programmable Logic Sequencer (PLS)

More complex

• FPGA (Field Programmable Gate Arrays)
• CPLD (Complex Programmable Logic Devices)

Classifications of Simple Programmable Logic Devices (SPLD)

Read Only Memory (ROM / PROM):

• N-input address lines, m-output data lines.
• Address lines point locations within ROM that store words of m bits.
• ROM size is defined by the no. of locations & the word size.
• A 256 X 4 ROM indicates that the device has 256 storage locations each holding a 4-bit word.
• This ROM would require eight address lines to access 256 locations.
• ROM of 32 X 8 has 32 memory locations each of 8-bit word and requires 5 address lines.
• Structure of ROM is as shown below; 

• So No. of address lines (Input Lines) = n. 
• No. of data lines (Output Lines) = m. 
• ROM size = 2n X m. 
• Size of decode which is to be used = n X 2n . 
• ROM Consists of an array of semiconductor devices interconnected to store an array of binary data. 
• Can’t be changed once burned in. 
• Conceptually, consist of a decoder and a memory array. 

Advantages: 

• Design become extremely easy. 
• It is possible to change or modify the design quickly. 
• Reduced cost. 
• Modification takes less time than SSI/MSI circuits. 

Disadvantages: 

• Increase in power requirement. 
• Complete circuit is not utilizes 
• Increase in size with increase in number of input variables. 

EXAMPLE 1: Tabulate the truth for an 8 X 4 ROM / PROM that implements the following four Boolean functions: 

A(X,Y,Z) = ∑m(1,3,4,6) 

B(X,Y,Z) = ∑m(2,4,5,7) 

C(X,Y,Z) = ∑m(0,1,5,7) 

D(X,Y,Z) = ∑m(1,2,3,4) 

ANS: Here, total No. of inputs are three 

• A,B,C Total No. of outputs are four
• A,B,C,D ROM size is = 8 X 4 So, according 2n X m 
• Inputs = n = 3, Output = m = 4, Size of Decoder = n X 2n = 3 X 8 

(Pending – diagram)

Here, * = Programmed Connection 

● = Fixed Connection 

EXAMPLE 2: What are functions F3, F2, F1 and F0 in terms of (A2, A1,A0) ? 

(Pending – diagram)

ANS: 

• F3 = D7 + D5 + D2 = A2A0 + A2’A1A0’ 
• F2 = D7 + D0 = A2A1A0 + A2’A1’A0’ 
• F1 = D4 + D1 = A2 A1’A0’ + A2’A1’A0 
• F0 = D7 + D5 + D1 = A2A0 + A1’A0 

EXAMPLE 3: Tabulate the truth for an 8 X 4 ROM / PROM that implements the following four Boolean functions: 

A(X,Y,Z) = ∑m(3,6,7); 

B(X,Y,Z) = ∑m(0,1,4,5,6) 

C(X,Y,Z) = ∑m(2,3,4); 

D(X,Y,Z) = ∑m(2,3,4,7) 

ANS: 

ROM size is = 8 X 4 So, according 2n X m 

Inputs = n = 3, Output = m = 4, 

Size of Decoder = n X 2n = 3 X 8 

Inputs are -> X,Y,Z 

Outputs are -> A,B,C,D

(Pending – table and diagram)

Programmable Array Logic (PAL): 

• PAL is most commonly used type of PLD. It is a programmable array of logic gates. 
• The array of logic gates is on single chip and it is in the AND-OR configuration. 
• The special feature of PLA is that a programmable AND array and fixed OR array. 
• Also note that in each OR gate in the OR array gets input from some of the AND gates. That means output of all AND gates are not applied to any of the OR gates  

• Un-programmed and programmed PAL are shown in below figure. 

(Pending – diagram)

Un-programmed PAL 

Programmed PAL 

• In Un-programmed PAL all the links are connected with Fusible Link as shown in below figure. 
• As per required output function one needs to burn the fusible link and this kind of PAL is known as a programmed PAL.

(Pending – diagram)

• Simplified representation of PAL is shown in below figure

Input Buffers: 

• Input buffer in a PAL is used for avoiding the loading of sources connected at the inputs. 
• The buffer produce inverted and non-inverted versions of their corresponding inputs. 
• One such buffer is used for each of the input lines as shown in above figure. 

AND Matrix: 

• AND matrix is shown as above figure. 
• The (X) mark indicate that a connection is present. Each AND gate has 2M input which are shown only by a single line (e.g. A,B,C, etc….). Where M is the No. of inputs. 
• When a logic function is to be implemented, we have to program the array. In programming the desired connections are left with the (X) marks and such mark is not used when connection is not required. 

OR Matrix: 

• OR matrix is shown as above figure. In PAL fixed OR array is used so there is no need to do programming to the OR array. 
• No. of OR arrays are equal to the required No. of functions at the output.

Input and Output Circuit: 

• The input and output circuit of PAL are similar to those PLAs. 
• The No. of fusible link in PAL is equal to 2M x n. where M = No. of available inputs and n = Corresponds to No. of product terms. 

Advantages: 

• For given internal complexity, a PAL can have larger N and M. 
• Some PALs have outputs that can be complemented, adding POS functions. 
• No multilevel circuit implementations in ROM (without external connections from output to input). PAL has outputs from OR terms as internal inputs to all AND terms, making implementation of multi-level circuits easier. 

Disadvantages: 

• n x m ROM guaranteed to implement any m functions of n inputs. PAL may have too few inputs to the OR gates. 

Designing steps of Combinational Circuits using PAL 

• STEP 1: Prepare the Truth Table. 
• STEP 2: Write a Boolean expression in SOP form. 
• STEP 3: Reduce / Find the Boolean expressions using K-map or reducing Boolean expression method. 
• STEP 4: List of product terms for each of the function and decide total No. of AND & OR gates required. 
• STEP 5: Decide connections of AND and OR matrix & draw logic diagram. 

NOTE: Out of first three steps, all three steps may not require in all examples 

EXAMPLE 1: A combinational circuit is defined by given truth Table for that Implement the circuit using PAL 

(Pending – table)

ANS: 

• STEP 1: Prepare the Truth Table. 

This step is not required in this example because it is given. 

• STEP 2: Write a Boolean expression in SOP form. 

This step is not required in this example

• STEP 3: Find the Boolean expressions using K-map or reducing Boolean expression method

• STEP 4: List of product terms for each of the function and decide total No. of AND & OR gates required. 

W = A + BD + BC 

X = BC’ 

Y = B + C 

Z = A’B’C’D + BCD + AD’ + B’CD’ 

Total No. of AND gate = 16 (B’cz maximum No. of product terms are in function Z (4 product terms) and total No. of functions are 4 so 4 X 4 = 16). 

Total No. of OR gates = Total No. of required functions at the output side (W,X,Y,Z) = 4. 

• STEP 5: Decide connections of AND and OR matrix & draw logic diagram 

• A PLD generally consist of programmable array of logic gates. Interconnections are made with the array inputs. 
• PLA consist two levels of logic, an AND-plane and an OR-plane, where both levels are programmable. 
• The outputs are connected to the device pins through inverting or non-inverting buffers and flip flops. 
• The basic block diagram of a PLA is shown in below figure. 
• Here programmable AND matrix can be used to implement the product terms in the SOP form and the programmable OR array can be used for implementing the sum of the product terms. 
• Logic gates used can be two level AND-OR, NAND-NAND or NOR-NOR configuration. Sometimes AND-OR-EXOR configuration is also used. But generally AND-OR is most preferable configuration. 
• Simplified representation of PLA is shown in below figure.

Input Buffers: 

• Input buffer in PLA is used for avoiding the loading of sources connected at the inputs. 
• Buffer of two types namely, inverted buffers and non-inverted buffers as shown in below figure. 
• One such buffer is used in each of the M input lines

AND matrix

• The X indicates that a connection is present. Each AND gate has 2M inputs which are shown only by single line where, M is No. of inputs (e.g. A,B,C, etc….). 
• When a logic function is to be implemented, we have to program the array. In programming the desired connections are left with the (X) marks and such mark is not used when connection is not required. 

OR Matrix: 

(Pending – circuit)

OR Matrix: 

• Above figure shows simplified representation of the OR matrix.  It is possible to program the OR matrix, by open circuiting the unwanted fusible links. The open fusible links are equivalent to a ‘0’ at the input of corresponding OR gate. 

• STEP 1: Prepare the Truth Table. 
• STEP 2: Write a Boolean expression in SOP form. 
• STEP 3: Reduce / Find the Boolean expressions using K-map or reducing Boolean expression method. 
• STEP 4: List of unique product terms. 
• STEP 5: PLA table implementation. 
• STEP 6: Decide connections of AND and OR matrix & draw logic diagram. 

NOTE: Out of first three steps, all three steps may not require in all examples 

EXAMPLE 1: Draw combinational circuit for a PLA with three inputs, three product terms and two outputs. 

ANS: 

Given, No. of inputs = 3 = I0, I1, I2 

            No. of Outputs = 2 = No. of OR gates. 

            NO. of product terms = No. of AND gates 

(Pending – circuit)

Difference between ROM, PAL and PLA.

(Pending – difference table)  

(Pending – Post MCQ)