Digital electronics : UNIT V

(Pending – Pre MCQ)

THEORY

Introduction 

Logic families represent kind of digital circuit/methodologies for logic expression 

Integration levels: 

SSI: Small scale integration 12 gates/chip MSI: Medium scale integration 100 gates/chip 

LSI: Large scale integration 1K gates/chip 

VLSI: Very large scale integration 10K gates/chip

ULSI: Ultra large scale integration 100K gates/chip 

Classification 

Logic Family 

Bipolar Logic Family 

1. Saturated 

• RTL(resistor transistor logic) 
• DCTL(direct coupled transistor logic) 
• IIL(integrated injection logic) 
• DTL(diode transistor logic) 
• HTL(high threshold logic) 
• TTL(transistor transistor logic) 

2. Non Saturated 

• Schottky TTL 
• ECL(emitter coupled logic) 

3. ULF(unipolar logic family) 

• PMOS(p-channel MOSFET) 
• NMOS(n-channel MOSFET) 
• CMOS 

Fan In 

• Fan in or gate is the number of inputs that can practically be supported without degrading practically input voltage level. 

 (Pending – diagram)

Fan in = 4 

Fan Out 

• The maximum number of digital input that the output of a single logic gate can feed and the gate must be same logic family. 
• Fan Out is calculated from the amount of current available in the output of a gate and the amount of current needed in each input of the connecting gate. 
• It is specified by manufacturer and is provided in the data sheet. 
• Exceeding the specified maximum load may cause a malfunction because the circuit will not be able supply the demanded power. 

(Pending diagram)

Fanout = 4 

Noise Margin 

• Noise is present in all real systems. This adds random fluctuations to voltages representing logic levels. 
• Hence, the voltage ranges defining the logic levels are more tightly constrained at the output of a gate than at the input. 
• Small amounts of noise will not affect the circuit. The maximum noise voltage that can be tolerated by a circuit is termed its noise immunity (noise Margin).  

Propagation Delay 

(Pending – diagram)

Transistor as a switch  

(Pending – diagram)

• A circuit that can turn on/off current in electrical circuit is referred to a switching circuit and transistor can be employed as an electronic switch 
• Cut off region – OFF State 
• Both junctions are reverse biased, Ic = 0 and V(BE) < 0.7 v 
• Saturation region 

Resistor Transistor Logic(RTL) 

• The basic RTL device is a NOR gate. 
• The inputs represent either logic level HIGH (1) or LOW (0). 
• The logic level LOW is the voltage that drives corresponding transistor in cut-off region, while logic level HIGH drives it into saturation region.
• If both the inputs are LOW, then both the transistors are in cut-off i.e. they are turned-off. Thus, voltage Vcc appears at output I.e. HIGH. 
• If either transistor or both of them are applied HIGH input, the voltage Vcc drops across Rc and output is LOW.

 (Pending – diagram)

(NOR GATE USING RTL)

Advantages of RTL Logic circuit:

The primary advantage of RTL technology was that it involved a minimum number of
transistors, which was an important consideration before integrated circuit technology, as
transistors were the most expensive component to produce

Limitations:

The obvious disadvantage of RTL is its high current dissipation when the transistor conducts to
overdrive the output biasing resistor. This requires that more current be supplied to and heat be
removed from RTL circuits. In contrast, TTL circuits minimize both of these requirements.
Diode Transistor Logic

• The diode-transistor logic, also termed as DTL, replaced RTL family because of greater
  fan-out
• capability and more noise margin.
• DTL circuits mainly consists of diodes and transistors that comprises DTL devices.
• The basic DTL device is a NAND gate.
• Two inputs to the gate are applied through diodes viz. D1, D2 . The diode will conduct only when corresponding input is LOW.
• If any of the diode is conducting i.e. when at least one input is LOW, the voltage at output keeps transistor T in cut-off and subsequently, output of transistor is HIGH. If all inputs are HIGH, all diodes are non-conducting, transistor T is in saturation, and its output is LOW.
  .

Due to number of diodes used in this circuit, the speed of the circuit is significantly low. Hence
this family of logic gates is modified to transistor-transistor logic i.e. TTL family which has been
discussed on next slide.  

(Pending – diagram)

Transistor Transistor Logic

• TTL family is a modification to the DTL. It has come to existence so as to overcome the speed limitations of DTL family. The basic gate of this family is TTL NAND gate. 
• Q3 is cutoff (act like a high RC ) when output transistor Q4 is saturated and Q3 is saturated (act like a low RC ) when output transistor Q4 is cutoff . Thus one transistor is ON at one time. 
• The combination of Q3 and Q4 is called TOTEM POLE arrangement. D D (DL AND GATE) (SATURATING INVERTER)
• Q1 is called input transistor, which is multi emitter transistor, that drive transistor Q2 which is used to control Q3 and Q4. 
• Diode D1 and D2 are used to protect Q1 from unwanted negative voltages and diode D3 ensures when Q4 is ON, Q3 is OFF. 

The output impedance is asymmetrical between the high and low state, making them unsuitable for driving transmission lines. This drawback is usually overcome by buffering the outputs with special line-driver devices where signals need to be sent through cables. ECL, by virtue of its symmetric low-impedance output structure, does not have this drawback.

Emitter Coupled Logic 

• ECL logic family implements the gates in differential amplifier configuration in which transistors are never driven in the saturation region thereby improving the speed of circuit to a great extent. The ECL family is fastest of all logic families. 
• Based on BJT, but removes problems of delay time by preventing the transistors from saturating. 
• Very fast operation – propagation delays of 1ns or less. 
• Low noise immunity of about 0.2-0.25 V . 
• The input impedance is high and the output impedance is low. As a result, the transistors change states quickly, gate delays are low, and the fan out capability is high. 

Function Table

(Pending – table)

Complimentary MOS (CMOS) 

• Considerably lower energy consumption than TTL and ECL, which has made portable electronics possible. 
• Most widely used family for large-scale devices o Combines high speed with low power consumption 
• Usually operates from a single supply of 5 – 15 V 
• Excellent noise immunity of about 30% of supply voltage 
• Can be connected to a large number of gates (about 50)  

Programmable Logic Circuit 

1. Hardwire System / Circuit 

• The operation of any circuit depends on IC chips used & electrical connection between chips.  No access to internal interconnections of IC chips. 
• To design circuit, internal circuit diagram is to be specified. 
• Once designed, the intended function can be performed. 
• If the function changes, design needs to modified. 
• So the internal circuit diagram needs to be changed. 
• Such systems are called HARDWIRED SYSTEM. 

2. Programmable Circuit 

• It uses programmable components. 
• Device includes arrays of logic elements on a chip & allows the user to specify or program many internal connections between these components on the chip. 
• Logic elements could be various gates, inverters, buffers and even flip flops. 
• A system function can be created on the chip, simply by programming the chip or telling the chip where the interconnections are to be made. 
• Such devices in general are called PROGRAMMABLE LOGIC DEVICE. 

3. Programmable Logic Devices (PLD):- 

• PLD is an IC chip that includes arrays of logic elements and allows a user to specify the connections among many of these elements. 

• Chip count & physical size of a system can be minimized. 
• Time from conception of system to marketing of the system can be minimized. 
• Less chip count leads to integration of system on a single chip or small no. of chips. 
• Low development cost. 
• Less space requirement. 
• High reliability. 
• Easy circuit testing. 
• Easy design modification. 

Disadvantages: 

• Interconnections between elements on the chip must be specified or programmed. 
• PLDs also have hard wired connection but they cannot function until they are programmed while Hardwired System functions.