LEVELS OF DESIGN DESCRIPTION in Verilog

The components of the target design can be described at different levels with the help of the constructs in Verilog.

1) Circuit Level

At the circuit level, a “switch” is the basic element with which digital circuits are built.
Switches can be combined to form inverters and other gates at the next higher level of abstraction.
Verilog has the basic MOS switches built into its constructs, which can be used to build basic circuits like inverters, basic logic gates, simple 1-bit dynamic and static memories.
They can be used to build up larger designs to simulate at the circuit level, to design performance critical circuits.

2) Gate Level

At the next higher level of abstraction, design is carried out in terms of basic gates. All the basic gates are available as ready modules called “Primitives“.
Each such primitive is defined in terms of its inputs and outputs. Primitives can be incorporated into design descriptions directly. Just as full physical hardware can be built using gates, the primitives can be used repeatedly and judiciously to build larger systems.
The gate level modeling or structural modeling as it is sometimes called is akin to building a digital circuit on a bread board, or on a PCB. One should know the structure of the design to build the model here. One can also build hierarchical circuits at this level.
However, beyond 20 to 30 of such gate primitives in a circuit, the design description becomes unwieldy; testing and
debugging become laborious.

3) Data Flow

Data flow is the next higher level of abstraction.
All possible operations on signals and variables are represented here in terms of assignments. All logic and algebraic operations are accommodated. The assignments define the continuous functioning of the concerned block.
At the data flow level, signals are assigned through the data manipulating equations. All such assignments
are concurrent in nature.
The design descriptions are more compact than those at the gate level.

4) Behavioral Level

Behavioral level constitutes the highest level of design description; it is essentially at the system level itself.
With the assignment possibilities, looping constructs and conditional branching possible, the design description essentially looks like a “C” program.
The statements involved are “dense” in function. Compactness and the comprehensive nature of the design description make the development process fast and efficient.

The Overall Design Structure in Verilog

The possibilities of design description statements and assignments at different levels necessitate their accommodation in a mixed mode. In fact the design statements coexisting in a seamless manner within a design module is a significant characteristic of Verilog.

Thus Verilog facilitates the mixing of the above-mentioned levels of design.

A design built at data flow level can be instantiated to form a structural mode design. Data flow assignments can be incorporated in designs which are basically at behavioral level.

CONCURRENCY in Verilog

In an electronic circuit all the units are to be active and functioning concurrently.

The voltages and currents in the different elements in the circuit can change simultaneously. In turn the logic levels too can change. Simulation of such a circuit in an HDL calls for concurrency of operation.
A number of activities – may be spread over different modules — are to be run concurrently here. Verilog simulators are built to simulate concurrency. (This is in contrast to programs in the normal languages like C where execution is sequential.)
Concurrency is achieved by proceeding with simulation in equal time steps. The time step is kept small enough to be negligible compared with the propagation delay values.
All the activities scheduled at one time step are completed and then the simulator advances to the next time step and so on.
The time step values refer to simulation time and not real time. One can redefine timescales to suit technology as and when necessary and carry out test runs.

In some cases the circuit itself may demand sequential operation as with data transfer and memory-based operations. Only in such cases sequential operation is ensured by the appropriate usage of sequential constructs from Verilog HDL.