Unit III
SEQUENTIAL CIRCUITS
Pre – MCQ
THEORY
The Basic Latch
- Basic latch is a feedback connection of two NOR gates or two NAND gates
- It can store one bit of information
It can be set to 1 using the S input and reset to 0 using the R input
The Gated Latch
- Gated latch is a basic latch that includes input gating and a control signal
- The latch retains its existing state when the control input is equal to 0
- Its state may be changed when the control signal is equal to 1. In our discussion we referred to the control input as the clock
- We consider two types of gated latches:
Gated SR latch uses the S and R inputs to set the latch to
1 or reset it to 0, respectively.
Gated D latch uses the D input to force the latch into a state that
has the same logic value as the D input.
(Pending – diagram)
Gated D Latch
(Pending – diagram)
Setup and Hold Times
- Setup Timetsu
The minimum time that the input signal must be stable prior to the edge of the clock signal.
- Hold Timeth
The minimum time that the input signal must be stable after the edge of the clock signal.
Flip-Flops
- A flip-flop is a storage element based on the gated latch principle
- It can have its output state changed only on the edge of the controlling clock signal
- We consider two types:
- Edge-triggered flip-flop is affected only by the input values present when the active edge of the clock occurs
- Master-slave flip-flop is built with two gated latches
- The master stage is active during half of the clock cycle, and the slave stage is active during the other half.
- The output value of the flip-flop changes on the edge of the clock that activates the transfer into the slave stage.
(Pending – diagram)
A Positive-Edge-Triggered D Flip-Flop
(Pending – diagram)
Master-Slave D Flip-Flop with Clear and Preset
(Pending – diagram)
T Flip-Flop
(Pending – diagram)
Excitation Tables
(Pending – table)
Sequential Circuit Design
- Steps in the design process
- State Diagrams and State Tables
- Steps in Design of a Sequential Circuit
- Specification – detailing of the inputs, the outputs, and the operation. Possibly assumes that have knowledge of digital system basics.
- Formulation: Generate a state diagram and/or a state table from the statement of the problem
- State Assignment: From a state table assign binary codes to the states.
- Flip-flop Input Equation Generation: Select the type of flip and generate the needed input
- Output Equation Generation: Derive output logic equations generation of the output from the inputs and current state.
- Optimization: Optimize the input and output equations. Today, CAD systems are typically used
- Technology Mapping: Generate a logic diagram of the circuit using ANDs, ORs, Inverters, and F/Fs.
- Verification: Use a HDL to verify the design
Registers and Counters
- An n-bit register is a cascade
- A counter can count occurrences
A Simple Shift Register
(Pending – diagram and table)
Parallel-Access Shift Register
(Pending – diagram)
Counters
- Counters are a specific type of sequential circuit.
- Like registers, the state, or the flip-flop values themselves, serves as the “output.”
- The output value increases by one on each clock cycle.
- After the largest value, the output “wraps around” back to0.
- Using two bits, we’d get something like this:
(Pending – table)
Benefits of counters
- Counters can act as simple clocks to keep track of “time.”
- You may need to record how many times something has happened.
– How many bits have been sent or received?
– How many steps have been performed in some computation?
- All processors contain a program counter, or PC.
– Programs consist of a list of instructions that are to be executed one after another (for the most part).
– The PC keeps track of the instruction currently being executed.
– The PC increments once on each clock cycle, and the next program instruction is then executed.
A Three-Bit Up-Counter
(Pending – circuit, table)
A Three-Bit Down-Counter
(Pending – circuit, table)
Shift registers:
In digital circuits, a shift register is a cascade of flip-flops sharing the same clock, in which the output of each flip-flop is connected to the “data” input of the next flip-flop in the chain, resulting in a circuit that shifts by one position the “bit array” stored in it, shifting in the data present at its input and shifting out the last bit in the array, at each transition of the clock input. More generally, a shift register may be multidimensional, such that its “data in” and stage outputs are themselves bit arrays: this is implemented simply by running several shift registers of the same bit-length in parallel.
Shift registers can have both parallel and serial inputs and outputs. These are often configured as serial-in, parallel-out (SIPO) or as parallel-in, serial-out (PISO). There are also types that have both serial and parallel input and types with serial and parallel output. There are also bidirectional shift registers which allow shifting in both directions: L→R or R→L. The serial input and last output of a shift register can also be connected to create a circular shift register Shift registers are a type of logic circuits closely related to counters. They are basically for the storage and transfer of digital data.
Buffer register:
The buffer register is the simple set of registers. It is simply stores the binary word. The buffer
may be controlled buffer. Most of the buffer registers used D Flip-flops.
(Pending – circuit)
The figure shows a 4-bit buffer register. The binary word to be stored is applied to the data terminals. On the application of clock pulse, the output word becomes the same as the word applied at the terminals. i.e., the input word is loaded into the register by the application of clock pulse.
When the positive clock edge arrives, the stored word becomes:
Q4Q3Q2Q1=X4X3X2X1 Q=X
Controlled buffer register:
- If goes LOW, all the FFs are RESET and the output becomes, Q=0000.
- When is HIGH, the register is ready for action. LOAD is the control input.
- When LOAD is HIGH, the data bits X can reach the D inputs of FF‘s. Q4Q3Q2Q1=X4X3X2 X1 Q=X
- When load is low, the X bits cannot reach the FF‘s.
Data transmission in shift registers:
(Pending – diagram)
A number of ff‘s connected together such that data may be shifted into and shifted out of them is called shift register. data may be shifted into or out of the register in serial form or in parallel form. There are four basic types of shift registers.
- Serial in, serial out, shift right, shift registers
- Serial in, serial out, shift left, shift registers
- Parallel in, serial out shift registers
- Parallel in, parallel out shift registers
Serial IN, serial OUT, shift right, shift left register:
Serial-in, parallel-out, shift register:
(Pending – diagram)