SEQUENTIAL MODELS In digital circuits, storage of data is done either by feedback, or by gate capacitances that are refreshed frequently. Pending : Fig.181 Sequential models FEEDBACK MODEL: Pending : Fig.182 Feedback Mode CAPACITIVE MODEL Pending : Fig.183Capacitive model When c becomes 1 the value of D is saved in the input gate of the […]
UNIT-V Sequential Circuit Description Component test and Verification Read More »
In today’s environment the MOS transistor is the basic element around which a VLSI is built. Designers familiar with logic gates and their configurations at the circuit level may choose to do their designs using MOS transistors. Verilog has the provision to do the design description at the switch level using such MOS transistors. Switch
UNIT-IV SWITCH LEVEL MODELLINGSYSTEM TASKS, FUNCTIONS, AND COMPILER DIRECTIVES Read More »
INTRODUCTION Design descriptions at data flow level and gate level are close to the circuit. At every stage of the design description process, one can relate the modules and the instantiations with the corresponding logic or sequential blocks and their interconnections. The approach is practical and effective as long
UNIT-III BEHAVIORAL MODELING Read More »
