Learn about SystemVerilog data types including integer, logic, real, nets, enums, strings, and more with examples and code snippets.

🔹 Introduction

SystemVerilog provides a rich set of data types that help in modeling both hardware and testbenches efficiently. Unlike older Verilog, it introduces strong typing, signed/unsigned control, and advanced user-defined types.

🔹 Integer Data Types

Common integer types in SystemVerilog include:

• bit – 2-state (0,1)
• logic – 4-state (0,1,X,Z)
• byte – 8-bit signed
• shortint – 16-bit signed
• int – 32-bit signed
• longint – 64-bit signed

// Example: Integer declarations
bit       b1;       // 2-state, 1 bit
logic     l1;       // 4-state, 1 bit
byte      a = 8'hFF;
int       count;
longint   big_num;

➡ Signed vs Unsigned

int a = -5;
bit [7:0] u = 8'hFF;   // unsigned
logic signed [7:0] s = -8'd5; // signed

🔹 Real Data Types

Used for floating-point numbers:

• real
• shortreal

real pi = 3.14159;
shortreal temp = 23.5;

🔹 Nets vs Variables

Nets (like wire, tri, etc.) represent physical connections. Variables (logic, int, etc.) hold values.

wire w1;
logic l1;
assign w1 = l1; // nets are driven by continuous assignments

🔹 Enumerated Types

Enums make code more readable and self-documenting, especially in FSMs.

typedef enum logic [1:0] {IDLE=2'b00, BUSY=2'b01, DONE=2'b10} state_t;
state_t curr_state;

🔹 String Data Type

SystemVerilog supports dynamic strings with built-in operators and methods.

string s1 = "Hello";
s1 = {s1, " World!"}; // concatenation
$display("Length = %0d", s1.len());

🔹 Events

event ev;
initial begin
  -> ev;         // trigger
  @ (ev);        // wait for event
end

✅ Key Takeaways

• Use bit for 2-state, logic for 4-state modeling.
• enum improves FSM readability and safety.
• Strings are dynamic and very useful in testbenches.
• Variables vs Nets distinction is important for RTL coding.