GLS Interview Q&A

Gate-level simulation (GLS) simulates a synthesised netlist of real standard cell instances and wires. RTL simulation simulates the behavioural HDL description.

• What is simulated: RTL uses abstract constructs. GLS uses cell instantiations (NAND2, DFFX1…) from the library.
• Timing: RTL has no timing. SDF-mode GLS uses real back-annotated delays from P&R.
• Scope: RTL checks functional intent. GLS checks that synthesis preserved it AND real delays do not violate timing.
• Scan chains: RTL has no DFT logic. GLS runs on the post-synthesis netlist with scan chains inserted.
• X-state: RTL X propagation can be optimistic. Gate-level X follows real gate truth tables.

STA is exhaustive for synchronous timing paths but has structural limitations:

• Asynchronous CDC: STA cannot analyse unconstrained clock domain crossings. GLS exercises them under real stimulus.
• False path misannotation: A wrong false path declaration is silently ignored by STA. GLS can still reveal the violation.
• Reset/power-up sequences: STA has no concept of reset order. GLS verifies correct initialisation across all power domains.
• Combinational glitches: STA characterises path delays but does not simulate time-domain waveforms. GLS propagates real edges and detects spurious pulses.
• DFT verification: Scan chains inserted post-synthesis do not exist in RTL. Only GLS verifies scan operation.

• Gate-level netlist: Post-synthesis or post-P&R Verilog/VHDL of cell instances and wires. Delivered by the backend team.
• Cell library simulation models: Verilog models for every cell type, including specify blocks. From the PDK.
• SDF timing file: Back-annotated IOPATH delays and timing check values from P&R or STA. Optional for zero-delay mode (suppressed with a warning).
• Testbench: Drives stimulus, instantiates DUT, checks outputs. May contain $sdf_annotate.

• Compile: Parse all HDL sources, check syntax and semantics, build module library cache.
• Elaborate: Build full design hierarchy. Apply SDF annotation here (not at simulation time). Compile specify blocks and timing file. Print annotation statistics.
• Simulate: Run testbench. Propagate transitions through cells using annotated delays. Evaluate timing checks at every clock edge. Report violations.

The design flow moves forward: RTL → synthesis → P&R → STA → silicon. Timing data is generated at the physical implementation stage, late in the forward flow.

Back-annotation takes that physical timing data and flows it backward to the verification stage. The SDF file carries this backward-flowing information. “Back” means: from physical implementation back to simulation. Without back-annotation, simulation would use only nominal cell delays — not the actual interconnect delays that dominate at advanced nodes.

A specify block in a cell model declares all timing information: module path delays (IOPATH — input to output propagation times), $setuphold (setup and hold requirements at flip-flop data inputs), $recrem (recovery and removal for async resets), and $width (minimum pulse width on clock pins).

It is the bridge between the SDF file and the simulator — the annotator matches each SDF entry to the corresponding specify block construct.

In zero-delay mode (-nospecify): the entire specify block is suppressed. Path delays and timing checks are both inactive. SDF annotation is also blocked. In SDF mode: the specify block default values are overwritten by the annotated SDF values.

• Post-synthesis (zero-delay): From first netlist. Functional regression, DFT, reset sequences. Fast — runs continuously in parallel with RTL regression.
• Post-P&R, typical corner: Development debug when first SDF delivered. Identifies annotation mismatches and obvious timing issues quickly.
• Slow corner (MAX delays): Setup time signoff milestone. Worst-case PVT — the manufacturing-relevant check.
• Fast corner (MIN delays): Hold time signoff. Parallel to slow corner.

EC formally proves the netlist is logically equivalent to the RTL. It is exhaustive for combinational Boolean equivalence and catches synthesis bugs that GLS might miss if coverage is incomplete.

EC cannot replace GLS because it has no concept of timing, reset sequences, scan chain operation, CDC crossings, glitch detection, or dynamic X propagation. It proves logical equivalence at a single point in time — not temporal correctness across a full simulation scenario.

The three tools (STA, EC, GLS) are complementary. Each covers specific verification categories the others cannot. Production tape-out requires all three.

• Zero delay (-nospecify): All specify blocks suppressed, no timing. Use post-synthesis for functional verification, DFT, reset checks. Fastest mode.
• Unit delay (+delay_mode_unit): All non-zero delays replaced with 1 time unit. Use to distinguish false races (disappear) from genuine races (persist). Breaks zero-delay feedback loops.
• SDF annotated: Real back-annotated cell and wire delays. The only mode detecting genuine setup/hold violations, glitches, and confirming operation at target frequency. Required for timing signoff.

Transport delay propagates every transition to the output shifted by the delay — including pulses narrower than the delay. Models an ideal wire.

Inertial delay rejects pulses narrower than the propagation delay. The pulse must persist long enough for the output capacitance to fully charge/discharge. Models real CMOS gate behaviour.

CMOS gates use inertial delay for cell path delays. Interconnect wires use transport delay. This combination is physically correct and is the simulator default.

When two signals change at exactly the same simulation time and all delays are zero, the simulator picks an arbitrary evaluation order. This can produce X or incorrect values that would never occur in silicon — a false race, caused by the simulation, not the design.

Identification: Switch to unit delay mode. If the X disappears → false race (the 1-unit delay separated the simultaneous events). If it persists → genuine race condition in the design that needs fixing.

Every SDF delay value is expressed as (minimum : typical : maximum) — three PVT corners. MTM control selects which value to use:

• MTM = MAXIMUM → worst-case slow corner → use for setup timing signoff
• MTM = MINIMUM → best-case fast corner → use for hold timing signoff
• MTM = TYPICAL → nominal corner → use for development debug

The same SDF file can be used for all three corners by changing only the MTM setting in the SDF command file.

• Slow corner (MAX): Paths take longest. Setup violations appear here — data arrives too late at the flip-flop before the clock edge. Failure → chip won’t run at target frequency at worst-case PVT.
• Fast corner (MIN): Paths are fastest. Data changes too quickly after the clock edge. Hold violations appear here. Hold violations are frequency-independent — they cannot be fixed by reducing clock speed.

Both must pass to guarantee correct operation across the full manufacturing PVT spread.

• pulse_r (reject limit %): Pulses narrower than this percentage of path delay are silently absorbed. No output transition, no warning.
• pulse_e (error limit %): Pulses between pulse_r% and pulse_e% are propagated as X and flagged with a warning.
• Pulses above pulse_e% propagate normally.

With pulse_r = 0, pulse_e = 0: every pulse shorter than the full path delay generates a warning and an X output — maximum sensitivity. Reports every potential glitch but floods the log. Use during focused glitch investigation.

• -nospecify: Suppresses everything in specify blocks — path delays AND timing checks. Also blocks SDF annotation. Signal transitions are instantaneous (zero delay). This IS zero-delay mode.
• -notimingchecks: Suppresses only timing check evaluation. Path delays remain fully active — waveforms show real annotated delays. Only the comparison against setup/hold thresholds is disabled.

An NTC delay arises when a $setuphold or $recrem check has a negative value — for example, setup = -20ps means data is allowed to change up to 20ps before the clock edge. At advanced nodes (7nm, 5nm, 3nm), cells are sized aggressively for setup time, and hold margin is “built in” to the cell’s internal structure, resulting in negative hold values.

The NTC algorithm handles these by generating internally delayed versions of clock and data signals (NTC delayed signals). The timing check is evaluated on these delayed signals instead of the primary inputs, preserving mathematical correctness.

NTC warnings (SDFNL2, NONTCTL, NTCNNC, etc.) arise when the algorithm encounters convergence issues — both values negative, or sum negative. The key question is always: did the algorithm converge? If yes, the timing check is working correctly despite the negative values.

• $sdf_annotate system task: Called in the testbench initial block at time 0. Arguments: SDF file path, scope, log file, MTM control.
• SDF command file: Plain-text file with SDF_FILE, SCOPE, MTM_CONTROL, LOG_FILE keywords. Passed via command-line switch at elaboration.

The SDF command file takes precedence. When both are present, $sdf_annotate is suppressed with a warning. This lets the same testbench serve both zero-delay GLS (no command file, $sdf_annotate suppressed by -nospecify) and SDF GLS (command file overrides).

The annotation scope is the hierarchical instance path from which SDF INSTANCE paths are interpreted as relative paths. If scope = tb_top.dut, then SDF instance u_cpu.g42 resolves to tb_top.dut.u_cpu.g42.

If the scope is wrong:

• Scope = testbench top instead of DUT → all path lookups skip the DUT level → PathDelays = 0%
• DIVIDER character mismatch (SDF uses ‘/’ but sim uses ‘.’) → all paths fail → 0% annotation
• Scope off by one level → partial annotation with SDFNEP warnings

Always examine SDF annotation statistics before looking at simulation failures or waveforms.

1. PathDelays %: Must be near 100%. Anything significantly below means wrong cell delays — do not trust timing results.
2. $setuphold %: Should be near 100% for primary timing check coverage.
3. Timing checks count in hierarchy summary: Must be non-zero. “Timing checks: 0” means specify blocks are inactive — -nospecify was applied or library has no specify blocks.
4. $hold / $width at 0%: Investigate once — may be expected (library uses $setuphold combined), or may indicate a format mismatch.

1. Timescale precision too coarse (most common): SDF TIMESCALE is 1ps but simulation runs at 1ns/1ns precision. 250ps = 0.25ns rounds to 0. Fix: -timescale 1ns/1ps or finer.
2. Module-level timescale override: Module has `timescale 1ns/1ns overriding command-line fine precision. Fix: add -override_precision.
3. SDFNEP/SDFNET on that specific path: Annotation failed for that arc; specify block default (0) is being used. Check elaboration log for warnings on the driving instance.
4. Genuinely zero in SDF: Annotation log shows IOPATH = (0:0:0) — zero came from the SDF itself. Report to backend for re-extraction.
5. Pulse rejection: Input pulse narrower than cell delay is absorbed by inertial delay — no output transition, appears as zero delay. Use -pulse_r 0 -pulse_e 0 to force propagation.

• ABSOLUTE: SDF values replace the specify block defaults entirely. Standard for P&R back-annotation — the SDF contains the complete delay (cell intrinsic + wire parasitics).
• INCREMENT: SDF values are added to the existing specify block values. Used when the SDF represents only the additional interconnect delay, with cell intrinsic already in the model.

• SDFNEP: IOPATH arc in the SDF (including edge qualifier) has no matching arc in the cell model’s specify block. Most common cause: SDF has conditional path (posedge A) but model has only unconditional path.
• SDFNET: Timing check in SDF does not match specify block. Most common: SDF has SETUPHOLD but model uses separate $setup + $hold statements.

Severity: sporadic SDFNEP on uncommon cells not on critical paths → medium priority, waive with documentation. Systematic SDFNEP on all instances of a common cell → high priority, fix the library/SDF. SDFNET where $setuphold still annotates at 100% → expected, waive. 0% on all checks → critical, do not use for signoff.

When the SDF has SETUPHOLD entries but the cell model uses separate $setup and $hold, the annotation cannot match — SDFNET fires. +sdf_splitvlog_suh instructs the annotator to split each SETUPHOLD in the SDF into separate $setup and $hold components for annotation.

Limitation: Only works when neither value in the SETUPHOLD is negative. If either is negative (NTC case), splitting is invalid — update the cell model instead.

TIMESCALE specifies the unit for all delay values in the SDF. If simulation precision is coarser, delays are silently rounded — potentially to zero. A 250ps delay at 1ns/1ns precision becomes 0.25ns → rounds to 0.

The insidious part: the annotator reports success and statistics show 100%, but the delays are zero in simulation. The only indicators are waveforms showing zero propagation delay, or a timing dump showing pdelay delay="0" for annotated arcs.

Rule: Simulation timescale precision must be ≤ SDF TIMESCALE. Use -override_precision if module-level timescales are coarser than the command-line setting.

1. CDC synchronisers: Designed to tolerate metastability — violations are intentional and expected, not bugs.
2. False paths: STA-declared false paths still generate GLS checks. The simulator cannot know the path is never exercised with timing-critical data.
3. Hard IP and memory macros: Third-party IP may have overly conservative checks; IP vendor may recommend disabling for GLS.
4. Performance: Timing check evaluation is expensive. Disabling checks on blocks already verified by STA reduces GLS runtime by 20–30%.

A timing file (tfile) is plain text, passed at elaboration. It configures timing checks per-instance or per-subtree with independent enable/disable settings.

• DEFAULT [+/-tcheck] — baseline for all unmatched instances
• PATH path [check_type] [+/-tcheck] — targets instance or subtree; ... matches all descendants
• CELLLIB lib timing_spec — all cells from a named library
• CELLINST timing_spec — all tagged cell instances and subhierarchy
• INCLUDE file — modular sub-team waiver files
• BASENAME path — prefix for subsequent PATH statements

The rule is one-directional:

• Works ✓: Cell model uses $setuphold. Tfile specifies PATH inst $setup -tcheck. → setup half of $setuphold is disabled, hold half active.
• Does NOT work ✗: Cell model uses separate $setup and $hold. Tfile specifies PATH inst $setuphold -tcheck. → no effect, both checks continue firing.

A combined keyword in the tfile matches combined checks in the model. But it cannot reach individual primitives.

Fix: To disable separate $setup and $hold, write two lines:

PATH top.u_ff $setup -tcheck
PATH top.u_ff $hold  -tcheck

Same rule applies to $recrem vs $recovery/$removal.

• Tfile (elaboration time): Prevents timing check infrastructure from being compiled. The check does not exist after elaboration → never evaluated at runtime → improves performance. Use for production waivers.
• tcheck (runtime): Check infrastructure is already compiled. Checks still evaluate every clock edge; only reporting and notifier updates are suppressed. No performance improvement. Use only for interactive debug.

-notimingchecks suppresses check evaluation but also prevents NTC delayed signals from being generated. In designs where cells have negative setup/hold values, NTC delayed signals drive downstream logic. If those signals are not generated, functional behaviour changes.

-ntcnotchks is safer because it:

• Generates NTC delayed signals → preserves correct functional behaviour
• Does NOT execute timing check evaluation
• Does NOT generate violation messages

Use -ntcnotchks on advanced-node designs with negative timing check values when suppressing violation messages without altering functional simulation behaviour.

• PATH top.u_cdc — targets only the exact instance top.u_cdc itself. Cells inside it are not affected.
• PATH top.u_cdc... — targets top.u_cdc and every instance in its entire subhierarchy, at any depth. All flip-flops and cells inside are affected.

Layered pattern used in production:

PATH top.u_cdc...    -tcheck   // disable CDC subtree
PATH top.u_cdc.u_arb +tcheck   // re-enable one instance

More specific paths override less specific ones. The re-enable for u_arb takes effect despite the parent -tcheck.

This is a zero-delay gate oscillation loop (TRZDGOC). A combinational feedback loop has no delay to break the cycle — every evaluation triggers another at the same simulation time, looping forever.

Resolution:

1. Add -gateloopwarn and -access +rwc at elaboration so the simulator can detect and interrupt the loop.
2. When halted, run drivers -active in TCL to identify the active driver in the loop.
3. Options: add -seq_udp_delay 1 (breaks loop in simulation), switch to unit delay mode, or fix the design if this is genuine combinational feedback.

CUVUNF means a hierarchical name in the testbench could not be resolved. It happens in GLS because synthesis flattens RTL hierarchy — sub-modules like u_alu are dissolved into their parent. The logic is preserved but the hierarchical boundary and internal net names are gone. A testbench reference to tb.dut.u_cpu.u_alu.carry_net fails because u_alu no longer exists.

Two resolutions:

• Immediate: Get the post-synthesis net name from the backend team and update the testbench.
• Preferred: Apply hierarchy preservation constraint in synthesis for the specific module. Note: preservation has 5–15% timing penalty on cross-boundary paths.

FLFFNF means the compiled SDF file specified in the SDF command file does not exist. Annotation is silently skipped — simulation runs with zero delays.

Happens when an SDF command file specifies COMPILED_SDF_FILE "timing.sdf.X" but the binary has not been generated, or is in a different directory.

Three fixes:

1. Use SDF_FILE "timing.sdf" (auto-compiles) instead of COMPILED_SDF_FILE — simplest for development.
2. Pre-compile with the SDF compiler tool, then reference with an absolute path.
3. Fix the path in the command file to point to where the binary actually exists.

Key question: does the waveform show the SDF-annotated delay?

1. Probe the output of the cell driving the failing flip-flop’s D input. Measure the propagation delay. Compare to the SDF value for that IOPATH arc.
2. Delay matches SDF → genuine failure. Report instance, SDF delay, and slack to backend for ECO.
3. Delay is zero or wrong → annotation problem. Search elaboration log for SDFNEP/SDFNET on the driving cell. Use -sdf_verbose and -dumptiming to confirm the annotated value.

This warning is specific to NTC delayed signals. When a flip-flop has a negative setup/hold value, the simulator creates internally delayed signal versions (e.g. DD for delayed data). If the NTC net has asymmetric rise and fall delays, and a new input event arrives before a scheduled output event can complete, the old event is cancelled. The warning reports this cancellation.

Debug: Add -ntc_verbose to see calculated rise/fall delays. Add $monitor on primary inputs to the affected net. If on a critical path → investigate before suppressing. If on a CDC path already in tfile → use -nontcglitch to suppress generation of the glitch event.

In zero-delay mode, “Timing checks” in the hierarchy summary must be 0. A non-zero count means timing checks are active when they should not be.

Possible causes:

• -nospecify was not actually applied — check the elaboration command carefully
• Testbench has a $sdf_annotate call that is executing despite intent — look for the SDFSKPA warning; if absent, the SDF is being annotated
• Cell library has timing checks coded outside the specify block (in initial/behavioral code) — not suppressed by -nospecify

Consequence: timing violation messages fire in zero-delay mode, failing tests for wrong reasons and hiding genuine functional failures.

1. Zero-delay GLS clean: All functional tests pass on the gate-level netlist. No CUVUNF errors. Scan chain tests pass.
2. SDF annotation ≥ target: PathDelays near 100%. All SDFNEP/SDFNET warnings resolved or formally waived with documentation.
3. Slow-corner GLS clean (setup): No unwaived timing violations at MAX delays. Remaining violations have backend ECO status or formal tfile waivers.
4. Fast-corner GLS clean (hold): No unwaived hold violations at MIN delays.
5. Tfile reviewed and approved: Every entry documented, reviewed by lead VE and design engineers. No blanket suppressions without justification.
6. Adequate test coverage: The regression suite exercising GLS has sufficient coverage — paths untested by GLS vectors are unchecked.

Flow: Backend delivers netlist+SDF → check annotation → run regression → categorise failures → fix or waive → repeat → signoff.

1. Testbench hierarchy error (CUVUNF): TB accesses flattened RTL path. Fixed by verification team — update TB net names.
2. Annotation warning (SDFNEP/SDFNET): SDF path not in cell model. Joint VE+backend investigation — may need library model update.
3. Genuine timing violation: Real setup/hold violation. Reported to backend team → ECO → new netlist/SDF → re-run.
4. Expected/known violation: CDC, false path, IP — confirmed acceptable. Added to tfile with justification. Verification team owns the waiver.

Zero-delay GLS speed (similar to RTL simulation) makes CI integration feasible. Each RTL commit triggers synthesis → new netlist → zero-delay GLS regression automatically:

• Catches synthesis bugs immediately: RTL change causing a functionally incorrect netlist fails within hours — not weeks later when manually kicked off.
• DFT issues caught early: Scan chain wiring errors from re-synthesis surface before they accumulate.
• CUVUNF appears immediately: Hierarchy changes breaking testbench references are caught at the commit that introduced them.
• Maintains a current GLS baseline: SDF GLS bring-up is faster when the team always has a working zero-delay run.

SDF GLS remains a scheduled milestone activity — its multi-day runtime makes CI impractical. But zero-delay GLS-in-CI is an established best practice at advanced-node SoC projects.

A violation at slow corner only could be genuine or an annotation artefact:

• Genuine: The slow corner is the signoff corner for setup timing. If the path barely meets timing at typical but fails at slow, the chip will fail at worst-case PVT in manufacturing. Cannot be waived just because typical passes.
• Artefact: An anomalous parasitic value in the slow-corner SDF causes one cell to show a disproportionately large delay. The waveform will show a delay that does not scale proportionally with other cells on the same path.

What to do:

1. Probe the slow-corner waveform — confirm each cell on the failing path shows the expected SDF-annotated delay.
2. Compare slow/typical ratio for the critical cell. Normal: 1.2–2x. Anomalous: 5x+ suggests extraction issue.
3. Normal ratio → genuine failure, report to backend for ECO.
4. Anomalous ratio → report the specific instance and arc to backend for SDF re-extraction. Do not waive without their confirmation.