Verilog Series Index — VLSI Trainers

Verilog Series

Verilog HDL — Complete Series

A structured, beginner-to-advanced guide to Verilog hardware description language. 18 posts covering every major concept from syntax to verification.

18Posts

7Chapters

HDLFocus

FreeAccess

Series Progress 18 of 18 posts published

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01 · Foundations 02 · Gate Level 03 · Data Flow 04 · Behavioral 05 · Data Types 06 · Switch Level 07 · System & Advanced

01Foundations

Introduction to Verilog

History, purpose, design flow, simulation vs synthesis. What Verilog is and why it exists.

Beginner Overview History

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Levels of Design Description

Switch level, gate level, dataflow, behavioral, and system level — how abstraction works in Verilog.

Beginner Abstraction Design Flow

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Language Constructs & Conventions

Identifiers, keywords, comments, whitespace, case sensitivity, and coding conventions.

Beginner Syntax Conventions

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Module in Verilog

Module declaration, port lists, port types, instantiation, hierarchical design, and parameter passing.

Beginner Module Hierarchy

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02Gate-Level Modelling

Gate-Level Modelling

Built-in gate primitives (and, or, nand, nor, xor, not, buf), gate instantiation, fan-in and fan-out.

Intermediate Gates Primitives

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Gate Arrays, Flip-Flops, Delays & Nets

Gate arrays, D/JK/T flip-flops from gates, rise/fall delays, min:typ:max, net types (wire, tri, wand, wor).

Intermediate Delays Nets Flip-Flops

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03Data-Flow Level Modelling

Data-Flow Level Modelling

Continuous assignments with assign, all Verilog operators, operator precedence, conditional expressions.

Intermediate assign Operators Expressions

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04Behavioral Modelling

Behavioral Modelling — Part 1

Procedural blocks (initial, always), blocking vs non-blocking assignments, sensitivity list, reg vs wire.

Intermediate always initial Blocking / Non-blocking

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Behavioral Modelling — Part 2

if-else, case/casex/casez statements, loops (for, while, repeat, forever), disable statements.

Intermediate case Loops Control Flow

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Behavioral Modelling — Part 3

Tasks and functions — definitions, calls, automatic vs static, differences, scope rules.

Intermediate Tasks Functions Scope

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Behavioral Modelling — Part 4

Named events, fork-join, inter-process timing, race conditions, simulation scheduling regions.

Advanced fork-join Events Timing

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05Data Types & Operators

Numbers, Strings, Data Types & Operators

Integer literals, real numbers, strings, reg/wire/integer/real/time types, all operators with precedence table.

Beginner Data Types Operators Literals

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06Switch-Level Modelling

Switch-Level Modelling

MOS transistor primitives (nmos, pmos, cmos), transmission gates, pull-up/pull-down, CMOS gates from transistors.

Advanced MOS Transistors CMOS

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Switch-Level Delays, Strengths & Trireg

Signal strengths (supply, strong, pull, weak, highz), charge storage with trireg, resistive switches, delay propagation.

Advanced Strengths trireg Charge

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07System Tasks, Parameters & Advanced

System Tasks & Functions

$display, $monitor, $strobe, $write, $finish, $stop, $time, $random, $readmemh, $dumpvars and more.

Intermediate $display $monitor File I/O

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System Tasks, Parameters & Path Delays

defparam, parameter overriding, specify blocks, path delays, timing checks (setup, hold, recovery), SDF annotation.

Advanced Parameters Timing Checks SDF

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Compiler Directives, Hierarchy & UDP

`define, `include, `ifdef/`ifndef, `timescale, hierarchical references, User-Defined Primitives (UDP).

Advanced `define UDP Hierarchy

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Functional Verification in VLSI

Verification planning, testbench structure, stimulus generation, self-checking testbenches, code coverage basics.

Advanced Verification Testbench Coverage

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