Complete APB Series Index — VLSI Trainers
APB Series · Complete Index

AMBA APB Protocol Series

A complete guide to the ARM Advanced Peripheral Bus — from the two-cycle transfer minimum to APB5 parity protection. Every signal, every state, every transfer type explained with timing diagrams and practical examples.

10
Posts
4
APB Versions
24
Signals
3
Operating States

The AMBA APB (Advanced Peripheral Bus) is the most widely deployed peripheral control interface in ARM-based SoCs. From Cortex-M microcontrollers to server-class Neoverse platforms, every chip has dozens of APB peripherals — UARTs, timers, GPIO controllers, interrupt controllers, SPI/I2C — all accessed through the same simple two-phase protocol.

This series walks through the complete ARM APB specification (IHI 0024E) from the very beginning. Each post is self-contained: you can read them in order to build from first principles, or jump to the specific topic you need.

Part 1 — Foundations
APB-01
Introduction to AMBA APB
What APB is, why it exists, AMBA hierarchy, Requester–Completer model, and the APB2→APB5 version timeline
Core
APB-02
Signal Descriptions
Every APB signal: PCLK, PRESETn, PADDR, PSELx, PENABLE, PWRITE, PWDATA, PRDATA — source, width, and purpose
Core
APB-03
Write Transfers
Setup and Access phases, write with no wait states, write with wait states, PREADY extension, signal stability rules
CoreAPB3
APB-04
Read Transfers
Read with no wait states, read with wait states, PRDATA timing, signal stability during Access phase
CoreAPB3
Part 2 — APB3 and APB4 Features
APB-05
Error Response — PSLVERR
When PSLVERR is valid, failing write and read transfers, register update behaviour on error, AXI/AHB error mapping
APB3
APB-06
Write Strobes — PSTRB
Byte lane mapping, sparse data transfer, PSTRB presence and Requester/Completer compatibility matrix
APB4
APB-07
Protection — PPROT and RME
PPROT[2:0] encoding (Normal/Privileged, Secure/Non-secure, Data/Instruction), PNSE for Realm Management Extension, compatibility rules
APB4APB5
Part 3 — APB5 Features
APB-08
Operating States — IDLE, SETUP, ACCESS
The three-state APB FSM, state transitions, signal requirements in each state, back-to-back transfers
Core
APB-09
Wake-up and User Signalling
PWAKEUP for clock gating, glitch-free requirements, PAUSER/PWUSER/PRUSER/PBUSER user-defined sideband signals
APB5
APB-10
Interface Parity Protection
Odd parity scheme, Check_Type property, all parity check signals (PADDRCHK, PCTRLCHK, PWDATACHK…), error detection behaviour
APB5
All APB Signals at a Glance
PCLK
Clock — all APB signals sampled on rising edge
APB2+
PRESETn
Active-LOW reset — synchronous to PCLK
APB2+
PADDR
Address bus — up to 32 bits, driven by Requester
APB2+
PSELx
Select — one per Completer, driven by Requester
APB2+
PENABLE
Enable — marks Access phase (2nd+ cycle)
APB2+
PWRITE
Direction — HIGH=write, LOW=read
APB2+
PWDATA
Write data — 8/16/32 bits, driven by Requester
APB2+
PRDATA
Read data — 8/16/32 bits, driven by Completer
APB2+
PREADY
Ready — Completer extends transfer when LOW
APB3+
PSLVERR
Transfer error — HIGH = error on last cycle
APB3+
PPROT[2:0]
Protection type — privilege, security, data/instruction
APB4+
PSTRB
Write strobe — one bit per data byte lane
APB4+
PWAKEUP
Wake-up — glitch-free activity indicator for clock gating
APB5
PNSE
RME extension — Root/Realm address space selector
APB5 RME
PAUSER
User request attribute — valid when PSELx asserted
APB5
PWUSER
User write data attribute
APB5
PRUSER
User read data attribute
APB5
PBUSER
User response attribute
APB5
How the Concepts Connect

Every transfer is two phases

  • Setup: PSELx=1, PENABLE=0 — address and control presented
  • Access: PSELx=1, PENABLE=1 — data transferred when PREADY=1
  • PREADY=0 during Access → additional wait state cycles inserted
  • PENABLE deasserted after every transfer completion

PREADY controls transfer duration

  • Completer drives PREADY LOW to add wait states
  • PADDR, PWRITE, PWDATA, PSTRB, PPROT must hold stable
  • No maximum on wait state cycles in the spec
  • Peripherals that never need wait states tie PREADY HIGH

PSLVERR only valid at transfer end

  • Valid only when PSEL, PENABLE, PREADY are all HIGH
  • Write error does NOT guarantee the register was NOT updated
  • Read error may return invalid PRDATA — requester may still use it
  • Maps to RRESP/BRESP on AXI, HRESP on AHB bridges

PPROT protection encoding

  • PPROT[0]: 0=Normal, 1=Privileged
  • PPROT[1]: 0=Secure, 1=Non-secure
  • PPROT[2]: 0=Data, 1=Instruction
  • PNSE + PPROT[1] selects: Secure/Non-secure/Root/Realm

APB state machine

  • IDLE → SETUP when transfer required (PSELx asserted)
  • SETUP → ACCESS always on next rising edge
  • ACCESS → IDLE if PREADY=1 and no next transfer
  • ACCESS → SETUP if PREADY=1 and next transfer to same peripheral

APB5 parity covers all signals

  • PADDRCHK, PCTRLCHK, PSELxCHK, PENABLECHK per control signal
  • PWDATACHK, PRDATACHK per 8-bit data lane
  • Odd parity — single parity bit for critical control signals
  • Check signals driven every cycle that Check Enable term is TRUE
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