AMBA APB Write Transfer Explained – Your VLSI Journey Starts Here

📋 The Two-Phase Transfer Model

Every APB transfer — read or write — follows the same two-phase structure. Understanding this structure is the foundation for everything else in the APB protocol.

Idle

PSELx = 0
PENABLE = 0
No transfer in progress

Setup Phase

PSELx = 1
PENABLE = 0
Address, control, data presented
Always exactly 1 cycle

Access Phase

PSELx = 1
PENABLE = 1
Transfer completes when PREADY = 1
1+ cycles (wait states if PREADY=0)

Idle / Next

PENABLE deasserted
PSELx deasserted (or new Setup)
Transfer done

The Setup phase always lasts exactly one clock cycle. There are no wait states during Setup — PENABLE is always asserted on the very next rising edge after PSELx. The Requester uses the Setup cycle to present the address, write data, and control signals to the Completer so the peripheral has one full cycle to decode the address and prepare for the transfer.

The Access phase lasts at least one cycle. If the Completer deasserts PREADY, additional cycles are inserted. There is no maximum on the number of wait state cycles — a peripheral could theoretically hold PREADY LOW indefinitely (though this would deadlock the system bus and is never done in practice).

At the end of the Access phase (when PREADY goes HIGH), PENABLE is deasserted. If another transfer to the same peripheral follows immediately, PSELx remains asserted and Setup begins again on the next cycle. If no further transfer is required, PSELx is also deasserted and the interface returns to IDLE.

⏱ Write with No Wait States

The simplest APB write: the Completer asserts PREADY in the first Access cycle, completing the transfer in exactly two clock cycles total.

Figure 1 — Write transfer with no wait states. T1: Setup phase begins — PSELx asserted, PADDR/PWRITE/PWDATA valid. T2: Access phase begins — PENABLE asserted, PREADY=1 immediately. T3: Transfer completes — write data accepted, PSELx and PENABLE deasserted.

Walking through each clock edge:

T1 (Setup phase starts): The bridge asserts PSELx. PADDR, PWRITE (HIGH for write), and PWDATA must all be valid at this point. PENABLE remains LOW — this is the Setup phase. The peripheral uses this cycle to decode the address.
T2 (Access phase starts): PENABLE is asserted. The bridge also asserts PREADY=1 (or the Completer already has it HIGH). All control and data signals remain stable. The transfer will complete at the next rising edge of PCLK (T3).
T3 (Transfer completes): On the rising edge of PCLK with PSELx=1, PENABLE=1, PREADY=1, the peripheral latches PWDATA into the addressed register. The bridge then deasserts PENABLE and PSELx (if no more transfers). The interface returns to IDLE.

⏱ Write with Wait States

A Completer that needs more than one Access cycle drives PREADY LOW during the Access phase. Each cycle with PREADY=0 inserts one wait state. The number of wait states is unlimited — the Completer can hold PREADY LOW for as many cycles as it needs.

Figure 2 — Write transfer with two wait states. T2: Access phase begins, PENABLE asserted. T3–T4: Completer holds PREADY=0, inserting two wait states. All bus signals (PADDR, PWRITE, PWDATA, PSELx, PENABLE) must remain completely stable. T5: PREADY asserted — transfer completes on this rising edge. T6: Interface returns to IDLE.

The key thing to understand about wait states: the entire APB bus is frozen while PREADY is LOW. Nothing changes — not the address, not the write data, not the direction, not the select or enable signals. The Completer is the only thing that can change state, and it does so internally while keeping PREADY LOW. When it is ready to accept the write, it drives PREADY HIGH and the transfer completes on the next rising edge.

The Requester (bridge) cannot abort a transfer once PENABLE is asserted. Once the Access phase has started, the bridge must hold all signals stable and wait for PREADY regardless of how long it takes. If a timeout mechanism exists, it is implemented in the bridge’s own logic — not in the APB protocol itself.

📋 Signal Stability Rules

The spec defines precisely which signals must remain stable during a write transfer. This is one of the most important rules for implementers — violating it causes undefined peripheral behaviour.

Signal	Must be stable from	Until	Notes
`PADDR`	Start of Setup phase	Transfer completes (PREADY=1)	Must not change during wait states
`PWRITE`	Start of Setup phase	Transfer completes	Must be HIGH for entire write transfer
`PSELx`	Start of Setup phase	Transfer completes	Must not be deasserted during wait states
`PENABLE`	Start of Access phase	Transfer completes	Already asserted; must stay asserted through wait states
`PWDATA`	Start of Setup phase	Transfer completes	Active write byte lanes must be valid and stable
`PSTRB`	Start of Setup phase	Transfer completes	APB4+ only; must stay stable like PWDATA
`PPROT`	Start of Setup phase	Transfer completes	APB4+ only; same stability requirement as PADDR
`PAUSER`	Start of Setup phase	Transfer completes	APB5+ only; must be same in Setup and Access
`PWUSER`	Start of Setup phase	Transfer completes	APB5+ only; write only; must be same in Setup and Access

The spec states these signals must be stable across all wait state cycles — not just between Setup and Access. A peripheral’s register write logic typically latches PWDATA on the cycle where PSELx, PENABLE, and PREADY are all HIGH. If PWDATA changes during a wait state, the peripheral’s latch would capture the wrong data.

PREADY can take any value when PENABLE is LOW. This means PREADY is irrelevant during the Setup phase. Peripherals that tie PREADY permanently HIGH are fully spec-compliant — they simply always complete in the minimum two cycles.

📋 Back-to-Back Write Transfers

When the APB bridge needs to write to the same peripheral on consecutive cycles, it can keep PSELx asserted and immediately start a new Setup phase after the previous transfer completes. This saves the one idle cycle that would otherwise occur between separate transfers.

Figure 3 — Back-to-back write transfers to the same peripheral. PSELx remains HIGH throughout. PENABLE is deasserted for one cycle at T3 (the Setup phase of transfer 2), then reasserted at T4 (Access phase of transfer 2). PADDR and PWDATA change at T3 to reflect the new transfer’s address and data.

The critical point: PENABLE must be deasserted between every transfer, even in back-to-back mode. The Setup phase is mandatory for every transfer. The Completer uses the deasserted PENABLE as the signal that a new transfer is beginning — it distinguishes a new write from a wait state of the previous write.

Back-to-back only works to the same Completer. If the second transfer targets a different peripheral, the bridge must also change PSELx — deassert the old Completer’s PSELx and assert the new one. Typically the bridge goes through one IDLE cycle between transfers to different peripherals, though the spec does not require it.

📋 APB2 vs APB3 Write Behaviour

The key difference between APB2 and APB3 write transfers is PREADY:

Aspect	APB2	APB3+
PREADY signal	Not present — Completer does not have this signal	Present — Completer drives PREADY
Transfer duration	Always exactly 2 cycles (fixed)	2+ cycles (variable, controlled by PREADY)
Wait states	Not possible — no mechanism to extend	Inserted by driving PREADY=0 during Access
Connection to APB3 bridge	Tie PREADY input HIGH at bridge. Default value = 1’b1.	Connect PREADY output from peripheral to bridge
Error reporting	Not possible — no PSLVERR signal	PSLVERR asserted with PREADY to signal error

When you have an APB3 bridge and an APB2 peripheral, the solution is always the same: tie the PREADY input for that peripheral’s slot to 1’b1. This makes the bridge behave as if PREADY is always asserted — effectively a two-cycle fixed transfer for every access to that peripheral.

📋 Quick Reference

Item	Rule
Minimum write transfer duration	2 cycles — one Setup + one Access with PREADY=1
Setup phase duration	Always exactly 1 cycle — no wait states during Setup
Access phase duration	1 cycle minimum; extended by 1 per PREADY=0 cycle
PENABLE during Setup	Must be LOW (deasserted)
PENABLE during Access	Must be HIGH (asserted) and remain HIGH through all wait states
PREADY during Setup	Irrelevant — can be any value; ignored by Requester
Transfer completes when	PSELx=1 AND PENABLE=1 AND PREADY=1 on rising PCLK edge
Signals stable during wait states	PADDR, PWRITE, PSELx, PENABLE, PWDATA, PSTRB, PPROT, PAUSER, PWUSER
APB2 peripheral with APB3 bridge	Tie PREADY=1 for that peripheral — fixed 2-cycle transfers
Back-to-back same peripheral	PSELx stays HIGH; PENABLE deasserted for 1 cycle (new Setup), then asserted again
Back-to-back different peripheral	PSELx changes; typically one IDLE cycle between transfers
Data latched by Completer at	Rising PCLK edge when PSELx=1, PENABLE=1, PREADY=1, PWRITE=1