Signal Descriptions

📋 Signal Overview and Notation

APB signals have a consistent naming convention. Understanding the convention tells you what a signal does before you even look it up.

• P prefix — all APB signals start with P (for Peripheral bus)
• Lowercase n suffix — active-LOW signal (e.g. PRESETn is active when LOW)
• x suffix on PSELx — there is one select signal per Completer; x is the instance number
• CHK suffix — APB5 parity check signal for the named payload signal

Some signals have a fixed width (PWRITE is always 1 bit). Others are parameterised by properties. When a property value is zero, the corresponding signal is not present on the interface. This is how APB handles optional signals — they simply don’t exist on interfaces that don’t need them.

⏱ Clock and Reset

PCLK — Clock

Source: system clock controller  |  Width: 1 bit  |  APB2+

PCLK is the clock for the entire APB domain. Every APB signal — from both the Requester and Completer — is sampled on the rising edge of PCLK. There are no asynchronous APB signals. All setup and hold timing requirements are defined relative to PCLK rising edge.

The APB clock domain may run slower than the main system bus (AXI/AHB). The APB bridge handles the clock domain crossing internally — from the software perspective, APB transfers always complete synchronously to PCLK.

PRESETn — Reset

Source: system bus reset  |  Width: 1 bit  |  APB2+

PRESETn is the active-LOW reset signal. It is normally connected directly to the system bus reset. When PRESETn is asserted (LOW), the APB interface is held in its reset state:

• PSELx must be deasserted (LOW)
• PENABLE must be deasserted (LOW)
• The state machine is in IDLE
• Completer output signals (PRDATA, PREADY, PSLVERR) should be driven to their default values

📋 Core APB2 Signals

These signals exist in every APB implementation from the original APB2 (2003) onwards. Every APB peripheral must have all of these signals.

PADDR — Address

Source: Requester  |  Width: ADDR_WIDTH (up to 32 bits)  |  APB2+

The APB address bus. Must be valid when PSELx is asserted and must remain stable throughout both the Setup and Access phases (including all wait state cycles). PADDR indicates a byte address. An unaligned address is permitted but the result is UNPREDICTABLE — a Completer may use the unaligned address, align it, or signal an error.

APB has a single address bus shared between reads and writes. Unlike AXI, there is no separate read address channel and write address channel.

PSELx — Select

Source: Requester  |  Width: 1 bit per Completer  |  APB2+

There is one PSELx signal per Completer. The Requester (APB bridge) asserts the appropriate PSELx to select the target peripheral for the current transfer. Only one PSELx is asserted at a time — the bridge decodes PADDR to determine which peripheral owns the addressed register and asserts only that peripheral’s PSELx.

PSELx being asserted marks the start of the Setup phase. It must remain asserted throughout the entire transfer (Setup + Access + all wait states).

PENABLE — Enable

Source: Requester  |  Width: 1 bit  |  APB2+

PENABLE distinguishes the Setup phase from the Access phase. It is deasserted during Setup (first cycle) and asserted during Access (second and subsequent cycles). The combination PSELx=1, PENABLE=0 means Setup phase. PSELx=1, PENABLE=1 means Access phase.

PENABLE is deasserted at the end of every transfer, even in back-to-back transfers between the same peripheral.

PWRITE — Direction

Source: Requester  |  Width: 1 bit  |  APB2+

Indicates the direction of the transfer. HIGH = write (Requester writes to Completer). LOW = read (Completer drives PRDATA to Requester). Must remain stable throughout the transfer.

PWDATA — Write Data

Source: Requester  |  Width: DATA_WIDTH (8, 16, or 32 bits)  |  APB2+

The write data bus, driven by the Requester when PWRITE is HIGH. Must be valid throughout both phases and all wait states. Not required to be valid during read transfers (when PWRITE=0), but the spec recommends driving it to zero when unused.

PRDATA — Read Data

Source: Completer  |  Width: DATA_WIDTH (same as PWDATA)  |  APB2+

The read data bus, driven by the selected Completer when PWRITE is LOW. Must be valid by the end of the Access phase (i.e., before the cycle in which PREADY goes HIGH and the transfer completes). The Completer must ensure PRDATA is stable when PSEL, PENABLE, and PREADY are all HIGH.

📋 APB3 Signals — PREADY and PSLVERR

APB3 added two signals that make peripherals much more practical to implement: PREADY allows variable-latency responses, and PSLVERR allows error reporting.

PREADY — Ready

Source: Completer  |  Width: 1 bit  |  Default (if absent): tie to 1  |  APB3+

PREADY is used by the Completer to extend the transfer duration. While PREADY is LOW during the Access phase, the transfer is frozen — all signals must remain stable and no state change occurs in either Requester or Completer.

• PREADY=1: Completer accepts the transfer this cycle. Transfer completes at the next rising edge of PCLK.
• PREADY=0: Completer is not ready. Transfer is extended by one more cycle. All bus signals must hold.
• PREADY when PENABLE=0: The value of PREADY is irrelevant during the Setup phase (when PENABLE=0). The spec states it can take any value — this allows simple peripherals to tie PREADY permanently HIGH.

PSLVERR — Transfer Error

Source: Completer  |  Width: 1 bit  |  Default (if absent): tie to 0  |  APB3+

PSLVERR allows the Completer to signal that the transfer completed with an error. PSLVERR is only valid during the last cycle of the transfer — when PSELx, PENABLE, and PREADY are all HIGH simultaneously. Its value at any other time must be ignored by the Requester.

• PSLVERR=0: Transfer completed successfully.
• PSLVERR=1: Transfer completed with an error.

Key behavioural rules for PSLVERR:

• A write error does not guarantee that the peripheral register was NOT updated. Whether the register was changed is peripheral-specific.
• A read error may return invalid PRDATA. There is no requirement to drive PRDATA to zero on an error.
• The Requester may still use PRDATA received alongside a read error — the Completer cannot rely on PSLVERR to prevent the requester reading PRDATA.
• Peripherals that do not implement error detection tie PSLVERR LOW permanently.

📋 APB4 Signals — PPROT and PSTRB

PPROT[2:0] — Protection Type

Source: Requester  |  Width: 3 bits  |  Default (if absent): 3’b000  |  APB4+

PPROT carries three independent protection attributes, one per bit:

PPROT must be valid when PSELx is asserted and must remain stable throughout the transfer. The primary use is PPROT[1] for secure/non-secure gating — peripherals in the secure world can reject transactions with PPROT[1]=1 (non-secure).

PPROT is optional on both Requester and Completer. If the Requester has PPROT but the Completer does not, the signal is simply not connected — the Completer has no access protection and accepts all transactions. If the Completer has PPROT inputs but the Requester does not, compatibility requires that fixed protection attributes be functionally correct (i.e., tie PPROT to the appropriate default).

PSTRB — Write Strobe

Source: Requester  |  Width: DATA_WIDTH/8 bits  |  APB4+

PSTRB enables sparse write data transfers — writing to only some byte lanes of a wide data bus. There is one PSTRB bit per 8-bit data lane: PSTRB[n] corresponds to PWDATA[(8n+7):(8n)].

• PSTRB[n]=1: The corresponding PWDATA byte lane contains valid write data.
• PSTRB[n]=0: The corresponding PWDATA byte lane should be ignored by the Completer.
• During reads: PSTRB must be driven ALL zeros. It has no effect on read transfers but must be driven to avoid undefined values.

📋 APB5 Signals — PWAKEUP, User Signals, PNSE

PWAKEUP — Wake-up

Source: Requester  |  Width: 1 bit  |  APB5

PWAKEUP indicates any activity associated with the APB Requester interface. It is designed to be routed to a clock controller so that peripherals and their clock domains can be powered up before a transfer begins.

Critical requirements for PWAKEUP:

• Must be glitch-free — generated from a register or a glitch-free OR tree
• Synchronous to PCLK
• Must remain asserted until PREADY is asserted, if PWAKEUP and PSELx are HIGH in the same cycle
• Recommended to be asserted at least one cycle before PSELx to avoid delaying transfer acceptance

PNSE — Realm Management Extension

Source: Requester  |  Width: 1 bit  |  Property: RME_Support=True  |  APB5 RME

PNSE extends PPROT[1] to create a four-value physical address space selector. Combined with PPROT[1]:

PNSE is only present when RME_Support=True and only on APB5 interfaces. If present, PPROT must also be present. PNSE must be valid when PSELx is asserted.

User Signals — PAUSER, PWUSER, PRUSER, PBUSER

APB5   All user signals are optional. If the associated width property is zero, the signal is absent.

📋 APB5 Parity Check Signals

APB5 defines a complete set of parity check signals for safety-critical applications (ISO 26262, IEC 61508). Each check signal provides odd parity coverage for one or more payload signals. They are present only when the Check_Type interface property is set to Odd_Parity_Byte_All.

Parity rules:

• Odd parity — there is always an odd number of 1s across the payload signal(s) and the check signal combined
• Each check bit covers no more than 8 payload bits
• Critical control signals (PSELx, PENABLE) get a single check bit — the inversion of the signal itself
• Check signals must be driven correctly every cycle in which their Check Enable condition is TRUE

📋 Signal Validity Rules

The APB spec (Appendix A) defines exactly when each signal must be valid. This is the complete ruleset:

📋 Complete Interface Diagram

📋 Quick Reference Table