PCIe 5.0, 6.0 — NRZ, PAM4, FEC and What Changed

⚡ The Bandwidth Trajectory

Every PCIe generation has approximately doubled the bandwidth per lane of the previous generation. Across eight generations spanning three decades this has produced a 128× bandwidth increase from the same physical connector and backward-compatible protocol stack. The challenge is that each doubling requires increasingly sophisticated signal integrity engineering at the Physical Layer.

📋 Gen 1 and Gen 2 — NRZ with 8b/10b

Gen 1 (2.5 GT/s) and Gen 2 (5 GT/s) use NRZ (Non-Return-to-Zero) signalling — the signal has exactly two levels: a logic-high voltage and a logic-low voltage. Each symbol carries one bit. The encoding is 8b/10b: every 8-bit data byte is mapped to a 10-bit code word before transmission. This 25% overhead (10 bits sent for every 8 bits of data) exists for three reasons:

• DC balance: 8b/10b ensures roughly equal numbers of 0s and 1s over any stretch of data. Without DC balance, capacitively-coupled receivers drift away from the correct threshold voltage. 8b/10b enforces that no more than 5 consecutive bits of the same value are ever sent.
• Clock recovery: the receiver’s CDR (Clock and Data Recovery) circuit recovers the bit clock from the signal’s transitions. Guaranteed transitions (from DC balance) ensure the CDR never loses lock due to long runs of identical bits.
• Special symbols: 8b/10b defines control characters (K-codes) outside the normal 256-byte data space, used for ordered sets, EIOS, EIEOS, COM, PAD, and other Physical Layer framing.

The effective data rate: Gen 1 at 2.5 GT/s with 8b/10b → 2.5 × 0.8 / 8 = 250 MB/s per lane per direction. Gen 2 doubles to 5 GT/s → 500 MB/s per lane per direction.

📋 Gen 3 — 128b/130b and Equalisation

Gen 3 doubles the bit rate to 8 GT/s but replaces 8b/10b with 128b/130b encoding. The motivation: at 8 GT/s, the 25% overhead of 8b/10b wastes too much bandwidth. 128b/130b adds only 2 bits per 128-bit block (1.5% overhead), recovering almost all of 8b/10b’s waste and effectively doubling the data throughput even without doubling the raw bit rate.

128b/130b works differently from 8b/10b:

• Data is grouped into 128-bit blocks. A 2-bit sync header is prepended, giving 130 bits on the wire.
• The 2-bit header is either 01b (data block) or 10b (ordered set block) — providing the guaranteed transitions for CDR. There are no longer K-codes for ordered sets; instead, 128-bit ordered set blocks replace them.
• Scrambling (LFSR-based) rather than 8b/10b lookup tables ensures DC balance and prevents repetitive patterns from causing electromagnetic emission issues.

Gen 3 also introduces 3-tap transmitter equalization (pre-cursor, cursor, post-cursor coefficients) and more aggressive receiver equalization (CTLE — Continuous Time Linear Equalizer) to compensate for channel loss at 8 GT/s. Training sequences exchange equalization presets using new TS1/TS2 fields during link training.

Effective data rate: 8 GT/s with 128b/130b → 8 × (128/130) / 8 ≈ 984 MB/s ≈ 1 GB/s per lane per direction.

📋 Gen 4 — 16 GT/s NRZ at its Limit

Gen 4 doubles to 16 GT/s while keeping the same NRZ modulation and 128b/130b encoding as Gen 3. The doubling required significant signal integrity improvements:

• More aggressive transmitter pre-emphasis and receiver equalization (DFE — Decision Feedback Equalizer added to CTLE)
• Tighter channel insertion loss budget
• Reduced trace length limits and stricter PCB stackup requirements
• Additional equalization preset search time during link training (more Tx presets, finer granularity)
• Improved reference clock specifications (reduced RMS jitter)

Effective data rate: 16 GT/s × (128/130) / 8 ≈ 2 GB/s per lane per direction. A x16 Gen 4 link delivers 32 GB/s bidirectional — sufficient for NVMe SSDs and NVIDIA A100-class GPUs.

Gen 4 reached 16 GT/s NRZ and was widely adopted. However, a further direct NRZ doubling to 32 GT/s without significantly more aggressive equalization would be impractical on standard add-in card trace lengths. Gen 5 achieved 32 GT/s NRZ by applying significantly more aggressive equalization (no RS-FEC, no PAM4). The true NRZ wall arrived at 64 GT/s — the point where even the best equalization cannot open the NRZ eye — which is why Gen 6 was the first generation to switch to PAM4 and to introduce RS-FEC.

📋 The NRZ Wall — Why NRZ Cannot Reach 64 GT/s

Gen 5 achieved 32 GT/s NRZ with aggressive equalization. But doubling again to 64 GT/s with NRZ is where the physics becomes prohibitive — two compounding effects make it impractical at standard PCB trace lengths:

The PAM4 solution for Gen 6: instead of doubling the symbol rate (which would push Nyquist to 32 GHz and close the NRZ eye), keep the symbol rate at 32 GBaud but carry 2 bits per symbol. PAM4 uses four voltage levels — each symbol encodes 2 bits. The Nyquist frequency stays at 32 GHz (same as a 64 GT/s NRZ link would require), but now each symbol carries 2 bits — achieving 64 GT/s effective bit rate with a manageable channel bandwidth. PAM4 is the only viable path to 64 GT/s on standard PCB channels.

📋 PAM4 — Four Voltage Levels Per Symbol

PAM4 (Pulse Amplitude Modulation with 4 levels) uses four distinct voltage levels to encode 2 bits per symbol. The four levels (named by their Gray coding): 00b, 01b, 11b, 10b from most negative to most positive. Because each transmitted symbol now carries 2 bits instead of 1, twice the data rate can be achieved at the same symbol rate (same Nyquist frequency).

PAM4 Gray coding

PAM4 uses Gray coding to map 2-bit dibit values to voltage levels. Adjacent voltage levels differ by only one bit: 11→10→00→01 (reading from top to bottom voltage level). Gray coding minimises the number of bit errors when the signal amplitude is misinterpreted as an adjacent level — the most likely error — because a one-level slip causes only a 1-bit error rather than a 2-bit error.

📋 PAM4 Eye Diagrams and Signal Integrity

A PAM4 eye diagram shows three eye openings (between the four voltage levels) rather than the single eye opening of NRZ. Each eye’s height is roughly one-third of the full voltage swing — making each eye significantly smaller than an equivalent NRZ signal at the same symbol rate. This is the fundamental trade-off of PAM4: twice the bit rate at the cost of a more demanding signal integrity requirement.

📋 Forward Error Correction — The FEC Solution

Forward Error Correction (FEC) is a technique where the transmitter adds redundant check symbols to the data stream. If some symbols are received incorrectly (due to noise, ISI, or crosstalk), the receiver uses the redundant symbols to detect and correct the errors — without any retransmission. “Forward” means the correction uses only the received data; no feedback to the transmitter is needed.

Why RS-FEC is necessary for Gen 6 PAM4 but not for Gen 1–5 NRZ:

• NRZ at Gen 1–5 achieves raw BER (Bit Error Rate) better than 10⁻¹² at the link layer after equalization — one raw error per trillion bits. This is acceptable without FEC because the LCRC (Link CRC) over a 4 KB TLP would fail only once every ~250 billion TLPs — a vanishingly rare event.
• PAM4 at 64 GT/s achieves raw BER of approximately 10⁻⁵ to 10⁻⁶ after equalization — far too many errors to forward to the Data Link Layer. Without FEC, the replay buffer would be constantly replaying TLPs, destroying throughput.
• FEC corrects these raw errors before they reach the Data Link Layer, restoring effective BER to better than 10⁻¹⁵ — below what any CRC-based retry scheme could tolerate.

📋 Reed-Solomon FEC in PCIe 6.0

PCIe 6.0 uses Reed-Solomon (RS) FEC. This is not used in Gen 5 — RS-FEC is specific to Gen 6’s PAM4 modulation, where the smaller eye opening produces far higher raw BER than NRZ links can tolerate. Reed-Solomon operates on symbols (bytes or multi-bit groups) rather than individual bits, making it particularly efficient at correcting burst errors — which is the dominant error pattern in PAM4 links where a momentary amplitude disturbance tends to corrupt several consecutive symbols.

FEC latency

RS-FEC adds latency at both the transmitter (must accumulate a full codeword before sending) and receiver (must receive and decode the full codeword before forwarding to the Data Link Layer). For PCIe Gen 6, RS-FEC latency is approximately 4–8 ns per link hop — a new source of latency that does not exist in Gen 1–5. For multi-hop topologies with switches, RS-FEC latency accumulates at each hop. This is why L0s exit latency is higher at Gen 6 compared to Gen 1–5 — each L0s exit must re-establish RS-FEC sync in addition to re-locking the CDR.

📋 Gen 5 — 32 GT/s NRZ with Advanced Equalization

PCIe 5.0 (ratified 2019) doubles Gen 4 bandwidth by pushing NRZ to 32 GT/s. Gen 5 does not use PAM4 and does not use Reed-Solomon FEC — it remains NRZ (two voltage levels, one bit per symbol), exactly like Gen 1–4. What makes 32 GT/s NRZ viable is significantly more aggressive equalization (additional DFE taps, stricter Tx pre-emphasis, tighter jitter budget) and 128b/130b encoding unchanged from Gen 3/4. Gen 5 is the last NRZ generation.

Key Gen 5 changes relative to Gen 4:

• NRZ modulation retained: Gen 5 keeps the same two-level NRZ signalling as Gen 1–4. One bit per symbol. The Nyquist frequency is 16 GHz — achievable on standard PCB channels with advanced equalization alone. No RS-FEC is required or used.
• No RS-FEC: Gen 5 does not use Reed-Solomon FEC. RS-FEC is a Gen 6 feature introduced specifically for PAM4. Gen 5 NRZ achieves sufficient raw BER through equalization alone — the LCRC and ACK/NAK replay mechanism in the Data Link Layer handles the rare residual errors just as in Gen 1–4.
• Encoding retained: Gen 5 keeps 128b/130b encoding from Gen 3/4. The 2-bit sync header per 128-bit block continues. Scrambling continues using the same LFSR polynomial.
• Equalization: more aggressive than Gen 4. Additional DFE taps, stronger CTLE gain, extended Tx pre-emphasis preset search during link training. This is the primary mechanism enabling 32 GT/s NRZ — not FEC.
• New Physical Layer Extended Capability: Physical Layer 32.0 GT/s Capability (Extended Cap ID 002Ah) for equalization status and FEC capability.
• Backward compatibility: Gen 5 hardware trains to Gen 4, Gen 3, Gen 2, or Gen 1 speeds when the link partner cannot match 32 GT/s. Full backward compatibility maintained.

Effective bandwidth: 32 GT/s NRZ × 1 bit/symbol × 128/130 (encoding overhead) / 8 = approximately 3.94 GB/s ≈ 4 GB/s per lane per direction. For a x16 Gen 5 link: 16 lanes × 2 directions × 4 GB/s = 128 GB/s bidirectional.

📋 Gen 6 — 64 GT/s PAM4 Physical Layer

PCIe 6.0 (ratified 2022) is the first generation to use PAM4. It doubles the bandwidth of Gen 5 NRZ by switching modulation: the symbol rate stays at 32 GBaud (same Nyquist frequency as Gen 5), but each symbol carries 2 bits instead of 1. The effective bit rate is 64 GT/s. Physical Layer changes relative to Gen 5:

• 64 GT/s symbol rate: each lane now clocks at 64 GBaud. Nyquist frequency: 32 GHz. Channel insertion loss budgets tighten further.
• RS-FEC (new in Gen 6): Reed-Solomon FEC introduced for the first time. Required because PAM4’s smaller eye opening produces raw BER around 10⁻⁵–10⁻⁶ — far worse than NRZ — which the LCRC+replay mechanism cannot handle alone. RS(272,258) with 14 parity symbols per codeword (5.1% overhead).
• New encoding: Gen 6 replaces 128b/130b with a flit-based framing at the Transport Layer (see below). The 1.5% overhead of 128b/130b is replaced with FEC overhead and flit header overhead.
• Tighter electrical specs: lower jitter budget, tighter output differential swing, improved receiver sensitivity required at 64 GT/s.
• Physical Layer 64.0 GT/s Capability: Extended Cap ID 002Ch for PAM4 equalization status, FEC state, and L0p capability.

Effective bandwidth: for a x16 Gen 6 link: 16 lanes × 2 directions × 8 GB/s = 256 GB/s bidirectional. The 8 GB/s per lane per direction accounts for FEC and flit overhead (approximately 93% efficiency).

📋 Flit-Based Transport Layer (Gen 6 Only)

Gen 6 introduces the most significant change to the PCIe protocol stack since Gen 3: a new flit-based (FLow unIt) Transport Layer that replaces the variable-length TLP-based framing used in Gen 1–5. This change is unique to Gen 6 and is designed specifically to improve efficiency at 64 GT/s.

In Gen 1–5, the Physical Layer sends: SKIP ordered sets (to compensate for clock differences) + framing tokens (SFRM, EFRM for each TLP) + the actual TLP header and data + LCRC. Each TLP is individually framed and CRC-protected. The overhead from framing tokens, SKIP ordered sets, and LCRC per TLP is small but meaningful at high symbol rates.

In Gen 6, the Physical Layer sends a continuous stream of fixed-size 256-byte flits. Multiple TLPs are packed into flits. A single flit may contain one large TLP, multiple small TLPs, or fractions of TLPs that span multiple flits. The CRC in Gen 6 (the RS-FEC check symbols) protects the entire flit — there is no per-TLP LCRC in flit mode.

📋 Flit Mode vs Standard TLP Mode

📋 Equalization — Tx and Rx

At Gen 5 and Gen 6 speeds, the channel (PCB trace + package trace + connector) causes severe inter-symbol interference (ISI) — a transmitted symbol’s energy spreads into adjacent symbol slots, distorting them. Equalization compensates for this distortion:

Equalization coefficients are negotiated during link training (the Gen 3+ equalization Phase 1/2/3 in the LTSSM Configuration and Recovery states). The link partner communicates its receiver’s preferred transmitter coefficients using TS1/TS2 fields. Gen 5/6 add more Phase iterations and a wider search space to find the optimal equalization operating point.

📋 Retimers and Redrivers

At Gen 5 and Gen 6 speeds, the PCIe channel insertion loss budget may not accommodate standard add-in card trace lengths (typically 12–20 cm on a motherboard plus a PCIe cable or riser). Retimers and Redrivers extend the channel reach:

PCIe-spec retimers (defined from Gen 3 onwards) are specification-compliant active devices that participate in the LTSSM training. They pass TS1/TS2 ordered sets and handle equalization negotiations on each segment independently, allowing the overall channel to be split into shorter segments each with manageable insertion loss.

📋 Backward Compatibility

PCIe’s most powerful feature across all generations is backward compatibility. A Gen 6 device connected to a Gen 3 system will train the link to Gen 3 speeds (8 GT/s, 128b/130b, no FEC, no flit mode) and operate fully. A Gen 3 device in a Gen 6 system trains the link to Gen 3 speeds. Neither device loses functionality — only bandwidth is limited to the common generation.

📋 Generation Comparison Quick Reference