Digital Memories

🏗️ Memory Hierarchy & VLSI Context

Digital memories form a hierarchy — faster memories are smaller and more expensive; slower memories are larger and cheaper. Every VLSI SoC implements multiple levels of this hierarchy on a single die or in a package.

📐 Memory Parameters

These six terms define how a memory unit behaves and are used on every datasheet:

📬 MAR, MBR, and Capacity Calculations

Every memory system has two key registers:

• MAR (Memory Address Register) — holds the address of the location being read or written. If the memory has 2ⁿ locations, MAR needs n bits.
• MBR (Memory Buffer Register) — holds the data being read from or written to memory. Its width equals the word length in bits.

💿 ROM — Read Only Memory

A ROM stores data permanently at manufacture time. It can be read but not written. The data is encoded in a 2D array (matrix) — the presence or absence of a transistor/diode at each intersection encodes a 1 or 0.

ROM Cell Technologies

🔥 PROM — Programmable ROM

A PROM is manufactured with all fuses intact (all bits = 1). The user programs it once by blowing selected fuses using a PROM programmer — high current pulses through the emitter fuse burn it open, storing a 0 at that cell. Once a fuse is blown it cannot be restored.

• Write: Once only — one-time programmable (OTP)
• Erase: Not possible — permanent
• Technology: Bipolar (fast) or MOS
• Use case: Field-programmable code storage, firmware that never changes, security keys

☀️ EPROM — Erasable PROM (UV Light)

Each EPROM cell is a floating-gate MOSFET. The floating gate is completely surrounded by silicon dioxide insulator. Programming injects high-energy electrons onto the floating gate using a high-voltage (12–25V) programming pulse — stored charge keeps the transistor permanently ON (bit = 0). Unprogrammed cells store bit = 1.

27xx EPROM Series

⚡ EEPROM — Electrically Erasable PROM

EEPROM (E²PROM) uses the same floating-gate MOS cell as EPROM but adds a very thin oxide region above the drain. This thin oxide (Fowler-Nordheim tunneling oxide) allows electrons to tunnel onto or off the floating gate electrically — no UV light needed.

🛠️ ROM Applications

Logic Function Implementation

Any Boolean function of n variables can be implemented directly in a 2ⁿ-word ROM. The n input variables are the address lines. The data stored at each address is the function output for that minterm. Multiple output functions (f₁, f₂, f₃…) share the same ROM — each uses one output data bit.

Look-up Tables

A 128×8 ROM implements sin(x): 7 address bits represent the angle in 1.4° steps (0–178.6°), and the 8 data bits represent the sine value scaled to 0–255. The processor looks up the precomputed value in one ROM read cycle — far faster than computing sin(x) in software.

Character Generators

A 5×7 dot-matrix character generator ROM stores the ON/OFF pattern of 35 dots for each ASCII character. Address = ASCII code; each row read gives 5 bits (one dot-row of the character). Used in early video terminals and alphanumeric displays.

Waveform / Function Generator

A ROM storing 256 samples of one sine wave cycle, addressed by an 8-bit counter, drives a DAC to produce a continuous analog sine wave. Frequency = f_CLK / 256. Change f_CLK to change the output frequency. This is the basis of Direct Digital Synthesis (DDS) — used in signal generators and software-defined radio.

🔄 RAM — Random Access Memory

RAM supports both read and write in equal access time. “Random access” means any location can be accessed directly in constant time — unlike sequential-access memories (tape, disk) where access time depends on current head position.

Linear Selection vs Coincident (X-Y) Selection

🔒 SRAM — Static MOS RAM Cell (6T)

The standard SRAM cell is a cross-coupled CMOS inverter pair (4 transistors: Q1–Q4) plus two access transistors (Q5, Q6) controlled by the word line (WL). Data is held statically as long as power is supplied — no refresh needed.

⚡ DRAM — Dynamic MOS RAM Cell (1T1C)

The DRAM cell uses just one transistor and one capacitor — far smaller than the 6T SRAM cell, enabling much higher density (Gb/chip vs Mb/chip). Data is stored as charge on the capacitor. The transistor acts as an access switch.

🔌 RAM ICs

IC 7489 — 16×4 Bipolar RAM

A simple 16-word × 4-bit bipolar RAM. Inputs: 4-bit address (select), Memory Enable (M̄Ē, active-low), Write Enable (W̄Ē, active-low). Output: 4-bit data (complemented — low output = stored 1). Useful for small fast lookup tables in SSI/MSI designs.

IC 2147 — 4K×1 Static NMOS RAM

A 4096-word × 1-bit SRAM. Separate Data In and Data Out pins. Chip Select (C̄S̄, active-low) activates the chip. Write Enable (W̄Ē, active-low) for write; C̄S̄ alone for read. Cascade 8 ICs for 4K×8 = 32 Kbit word-wide RAM.

IC 4164 — 64K×1 Dynamic NMOS RAM

A 65,536-word × 1-bit DRAM. The 16-bit address is multiplexed over 8 address pins using RAS (Row Address Strobe) and CAS (Column Address Strobe). The memory is organised as a 256×256 matrix — 8 RAS bits address 256 rows, 8 CAS bits address 256 columns.

📦 Expanding RAM — Word-Width and Address Space

Increasing Word Width (Parallel Connection)

Connect multiple RAM ICs in parallel, sharing the same address and control lines, but each contributing its own data bits. Two 7489 (16×4) ICs connected in parallel = 16×8 RAM — the address lines of both ICs are tied together; one IC provides bits b₇–b₄, the other provides b₃–b₀.

Increasing Address Space (Series Connection with Decoder)

To expand the number of addressable words, use a decoder driven by the extra address bits to select which IC’s Chip Select is active. Example: four 1K×8 PROMs + 2-to-4 decoder = 4K×8 ROM. Each PROM handles 1K addresses; the 2-bit MSB selects which PROM is active via the decoder’s output connecting to each IC’s Chip Enable (C̄Ē).

💾 Magnetic Memories

Magnetic Core Memory

A toroidal ferrite core stores one bit as the direction of magnetic flux (clockwise = 0, counter-clockwise = 1). The hysteresis curve is nearly rectangular — the core snaps between ±Φ_m with no intermediate states. Reading is destructive — the read current drives the core to −Φ_m to sense the change; a rewrite must follow immediately. Used in mainframes through the 1970s. Non-volatile (data survives power-off).

Magnetic Disk — Data Encoding Standards

Floppy Disk

5.25-inch floppy: 77 tracks × 26 sectors × 128 bytes/sector = 256 KB total. The plastic jacket protects the flexible Mylar disk. The index hole provides the angular reference. A write-protect notch prevents accidental overwriting when covered with tape. Average access time ~500 ms — slow by modern standards but revolutionary in the 1970s–80s.

Hard Disk

Rigid aluminium platters coated with magnetic material, stacked on a rotating spindle at 3600–5400 RPM. The read/write heads float on an air cushion ~100 nm above the surface. Data transfer rates: 1–10 Mb/s (early HDD). Modern HDDs achieve 200–300 MB/s with 10+ TB capacity using perpendicular magnetic recording (PMR) and heat-assisted magnetic recording (HAMR).

💡 Bubble Memory, CCD, and CD-ROM

Magnetic Bubble Memory

Cylindrical magnetic domains (“bubbles”) in garnet material represent data — bubble present = 1, absent = 0. Bubbles are moved along predefined tracks by a rotating magnetic field (no mechanical motion). Capacity up to 1 Mb/chip. Non-volatile, solid-state, highly reliable — but slow access. Used in specialised industrial/military applications. Largely obsolete — superseded by Flash.

Charge Coupled Devices (CCD)

Data stored as charge packets in capacitor arrays. Charge shifts from cell to cell on each clock pulse — sequential access only (not random). Must be refreshed like DRAM. Used in imaging sensors (CCD cameras) rather than data storage today. Access time is not constant.

CD-ROM (Optical Memory)

650 MB capacity on a 120 mm polycarbonate disc coated with reflective aluminium. Data encoded as microscopic pits (≈ 0.83 µm diameter) and lands on a spiral track. Pits are created by a high-intensity laser on the master disc; copies stamped in bulk. Reading uses a low-power laser — a pit-to-land or land-to-pit transition = 1; no transition within a stretch = 0. Rotates at 360 RPM with constant linear velocity (CLV). Entirely read-only (hence ROM in the name).

📋 Quick Reference

ROM Family Comparison

RAM Comparison

Memory Parameters Formula Sheet