Complete UVM Series Index — VLSI Trainers

UVM Series · Complete Index

Universal Verification
Methodology — UVM

A complete, structured course on Universal Verification Methodology. From your first testbench component through Register Abstraction Layer, sequences, scoreboards, factory overrides, and debug. Every concept explained with timing diagrams, architecture figures, and working SystemVerilog code.

30

Posts

6

Parts

UVM

IEEE 1800.2

100%

Practical Code

Every post is a self-contained explainer with architecture figures, signal-level timing, and working SystemVerilog code. Read in order to build from first principles, or jump to any topic you need.

Prerequisites: solid SystemVerilog (classes, interfaces, randomisation, coverage). If you need to brush up, work through the SV Series first.

Part 1 Testbench Architecture

Introduction to UVM

What UVM is, why it exists, the UVM class library overview, uvm_component vs uvm_object, and the standard testbench topology from test to driver

Testbench Architecture

The standard UVM testbench hierarchy: test → env → agent → sequencer/driver/monitor. uvm_component tree, parent-child relationships, and dot-path names

Build, connect, run, report phases — execution order, top-down vs bottom-up, task phases vs function phases, phase objections, and common phase mistakes

The UVM Factory

Type registration with `uvm_component_utils and `uvm_object_utils, create() vs new(), factory overrides, why the factory matters for reuse and configurability

Active vs passive agents, uvm_agent internals, is_active flag, building sequencer+driver+monitor inside the agent, agent configuration object pattern

Block-Level Testbench

Building a complete block-level testbench step by step: test class, env, agent instantiation, virtual interface assignment, run_test() hook, and wiring it all together

Part 2 Connections & Configuration

Virtual Interfaces

Why virtual interfaces are needed, declaring and passing virtual interfaces from the SV top module, virtual interface handle in config objects, the two-kingdom problem

set() and get() API, hierarchical path wildcards, type-parameterised database, passing virtual interfaces and config objects, common pitfalls and debug

Configuration Objects

uvm_object-based config, nested config hierarchies, parameterised tests, config objects vs config_db, ConfigDB vs package pattern, sequence configuration

Factory Overrides in Practice

Type overrides vs instance overrides, override in test build_phase, abstract/concrete component pattern, Bus Functional Model substitution, TwoKingdoms factory

ConnectAdvanced

Part 3 Sequences & Stimulus

uvm_sequence_item, fields and constraints, `uvm_field macros, do_copy / do_compare / do_print / convert2string, randomisation and directed overrides

Sequences — Basics

uvm_sequence body() task, start_item / finish_item handshake, sequence-sequencer-driver flow, randomise-before-send pattern, sequence API

uvm_driver internals, get_next_item / item_done, unidirectional vs bidirectional vs pipelined driver models, response items, drive-then-wait pattern

Virtual Sequences & Sequencers

Virtual sequence concept, virtual sequencer, running multiple sequences in parallel, sub-sequencer handles, multi-agent coordination, layered sequences

SequencesAdvanced

Sequence Control & Arbitration

Sequencer arbitration modes, sequence priority, lock/grab, sequence overrides, sequence libraries, stopping sequences, signal-level wait in sequences

SequencesAdvanced

Interrupt Handling & Slave Sequences

Handling DUT-generated interrupts in sequences, interrupt service sequences, slave sequencer responding to DUT requests, reactive agents

SequencesAdvanced

Part 4 Analysis, Scoreboards & Coverage

TLM Analysis Ports

uvm_analysis_port, uvm_analysis_imp, write() method, broadcast to multiple subscribers, analysis FIFO, connecting monitor to scoreboard and coverage

uvm_monitor design, passive observation of DUT interfaces, transaction assembly from signal activity, publishing to analysis port, reuse across testbenches

Scoreboards & Predictors

Reference model pattern, uvm_scoreboard, in-order vs out-of-order checking, predictor component, comparison methods, error reporting, metric analysis

Functional Coverage

Covergroups in UVM components, sampling from analysis ports, coverage collector class, coverage-driven verification closure, post-run phase reporting

End-of-Test Mechanisms

raise_objection / drop_objection, phase objection drain time, uvm_test_done, automatic objections, common deadlock scenarios and how to avoid them

Part 5 Register Abstraction Layer (RAL)

RAL Introduction

Why RAL exists, uvm_reg_block and uvm_reg hierarchy, frontdoor vs backdoor access, the adapter pattern, integrating RAL with an existing testbench

Building the Register Model

uvm_reg fields, uvm_reg_map, register model structure, RO/WO/RW/RC/RS access types, quirky registers (write-1-to-clear, toggle, aliased), model coverage

RAL Adapter & Integration

Writing a uvm_reg_adapter for your bus protocol, reg2bus() / bus2reg(), connecting the register model to the DUT, frontdoor read/write sequences

RAL Stimulus & Built-in Sequences

Using read()/write() from sequences, mem_walk_seq, reg_bit_bash_seq, reg_access_seq, backdoor access via HDL paths, register scoreboarding and coverage

Part 6 Debug, Advanced Topics & Practical

UVM Reporting & Debug

`uvm_info / `uvm_warning / `uvm_error / `uvm_fatal, verbosity levels, +UVM_VERBOSITY, uvm_report_server, command-line processor, message filtering

UVM Command Line & Plusargs

uvm_cmdline_processor, +uvm_set_config_int, +uvm_set_config_string, +uvm_testname, custom plusargs, runtime test selection and configuration

Integration-Level Testbench

Multi-agent environments, env-of-envs, integration-level topology, connecting multiple protocol agents, reusing block-level UVCs at chip level

UVM Coding Guidelines

Naming conventions, file and package organisation, when to use macros vs manual implementation, UVM do’s and don’ts from industry best practices

Complete UVM Testbench — End to End

Full worked example: APB GPIO DUT, complete UVM testbench from scratch — agent, sequences, monitor, scoreboard, RAL, coverage, and 3 test scenarios with EDA Playground code

UVM Base Classes at a Glance

uvm_component

Persistent testbench components. Has phases, parent, path. Base of all agents, drivers, monitors.

uvm_object

Transient data objects. No phases. Base of sequence items, sequences, config objects.

uvm_sequence

Extends uvm_sequence_base. body() generates items. Runs on a sequencer.

uvm_driver

Extends uvm_component. Pulls items from sequencer, drives DUT via virtual interface.

uvm_monitor

Extends uvm_component. Observes DUT signals, assembles transactions, publishes to analysis port.

uvm_scoreboard

Extends uvm_component. Receives transactions via analysis imp. Compares actual vs expected.

uvm_agent

Container for sequencer+driver+monitor. is_active flag. Active or passive mode.

uvm_env

Top-level container. Holds agents, scoreboards, coverage collectors. Extended per DUT.

uvm_test

Extends uvm_component. build_phase creates env. run_phase starts root sequence. One per scenario.

uvm_reg_block

RAL register model root. Contains uvm_reg instances, uvm_reg_map, and memory map.

uvm_reg

Single register model. Contains uvm_reg_field instances. Provides read()/write() methods.

uvm_reg_adapter

Protocol bridge for RAL. reg2bus() / bus2reg() converts between uvm_reg_bus_op and sequence items.

How the Concepts Connect

Testbench is a tree of uvm_components

test → env → agent → driver/monitor/sequencer
Each node created in parent’s build_phase
Factory creates every component — enabling overrides
Dot-path names used for config_db lookup

Phases control execution order

build/connect run top-down / bottom-up (functions)
run_phase runs concurrently in all components (task)
objections keep simulation alive until all dropped
post-run phases for reporting and cleanup

Stimulus flows: sequence → driver → DUT

body() calls start_item / finish_item per item
Sequencer arbitrates between concurrent sequences
Driver calls get_next_item / item_done per item
Virtual sequences coordinate across multiple agents

Observation flows: DUT → monitor → analysis

Monitor samples DUT signals, assembles transactions
analysis_port.write() broadcasts to all subscribers
Scoreboard compares actual vs predicted transactions
Coverage collector samples covergroups from transactions

Configuration propagates through config_db

Test creates config objects, sets them with full path
Components retrieve config with their component path
Virtual interface passed from SV top via config_db
Factory overrides change component types at runtime

RAL abstracts register access

Register model mirrors DUT register map
Adapter converts reg operations to bus transactions
Frontdoor = via bus; Backdoor = direct HDL force/read
Built-in sequences test every register automatically

Start the Series → UVM-01: Introduction to UVM