AMBA APB Read Transfer Explained – Your VLSI Journey Starts Here

📋 Read vs Write — What Changes

A read transfer follows the same two-phase structure as a write transfer. The Setup and Access phases, the PREADY extension mechanism, and the signal stability rules are all identical. Only three things change between a read and a write:

Write Transfer

PWRITE = 1 (HIGH)
Requester drives PWDATA with data to write
PSTRB indicates which byte lanes are valid
Completer does not drive PRDATA
Data flows Requester → Completer

Read Transfer

PWRITE = 0 (LOW)
Completer drives PRDATA with register contents
PSTRB must be driven all-zero by Requester
PWDATA is not required to be valid
Data flows Completer → Requester

Everything else is the same: PSELx, PENABLE, PADDR, PPROT, PAUSER all behave identically in both read and write transfers. PREADY is still driven by the Completer to control the number of cycles. PSLVERR is still valid only at transfer completion.

PWRITE must be stable for the entire transfer duration. You cannot change the direction mid-transfer. A transfer is either fully a read or fully a write — there is no partial read/write in APB.

⏱ Read with No Wait States

The simplest APB read: the Completer provides PRDATA before the end of the Access phase and asserts PREADY in the first Access cycle. Total transfer time: two clock cycles.

Figure 1 — Read transfer with no wait states. PWRITE is LOW throughout. The Completer drives PRDATA stable during the Access phase. PRDATA must be valid by T3 (the rising edge where PSEL+PENABLE+PREADY are all HIGH). The Requester captures PRDATA at T3.

Step by step:

T1 (Setup phase): Bridge asserts PSELx and drives PADDR to the target register address. PWRITE is driven LOW — this is a read. PENABLE remains LOW. The peripheral decodes the address and begins preparing the register value.
T2 (Access phase starts): PENABLE is asserted. PREADY is HIGH (Completer is ready). The peripheral drives PRDATA with the contents of the addressed register. All control signals remain stable.
T3 (Transfer completes): Rising PCLK edge with PSELx=1, PENABLE=1, PREADY=1. The bridge samples PRDATA on this edge. PSELx and PENABLE are deasserted. PRDATA is no longer required to be valid after this edge.

⏱ Read with Wait States

When the Completer needs extra time to retrieve the register value — for example, if the read requires a slow memory access or a calculation — it drives PREADY LOW during the Access phase to insert wait states.

Figure 2 — Read transfer with two wait states. PRDATA is undefined (hatched region) during the wait state cycles T2–T4 — the Completer is still computing or fetching the value. At T5 PREADY is asserted and PRDATA must be valid. The Requester samples PRDATA on the T5 rising edge.

The key difference from a write with wait states: PRDATA is only required to be valid at the cycle when PREADY is asserted. During wait state cycles the Completer is preparing the data — PRDATA can be anything (though it should not be actively driven to misleading values). The Requester must not sample PRDATA until the completion cycle.

PRDATA is undefined during wait states — the Requester must wait for PREADY. A common bug in APB bridge implementations is sampling PRDATA on the first Access cycle instead of on the PREADY=1 cycle. For zero-wait-state peripherals these happen to be the same cycle so the bug goes undetected until a slow peripheral is connected.

📋 PRDATA Timing Requirements

PRDATA has stricter timing requirements than PWDATA because it flows from Completer to Requester (the direction opposite to all other data). Understanding the timing window is critical for both peripheral designers and bridge designers.

Figure 3 — PRDATA validity window. The Completer must ensure PRDATA is valid (meets setup time) before the rising clock edge at which PREADY is asserted. Before that edge, during wait states, PRDATA may be undefined.

What the Completer must do

Ensure PRDATA is driven and meets the setup time of the Requester’s input flop at the rising edge where PREADY is asserted.
PRDATA must be driven with the correct register value — it cannot be left high-impedance or driven with stale data from a previous transfer.
PRDATA should be held stable until at least after the completion edge so the Requester can reliably capture it.

What the Requester (bridge) must do

Sample PRDATA only on the rising edge of PCLK where PSELx=1, PENABLE=1, PREADY=1, and PWRITE=0.
Never sample PRDATA on any other cycle — including wait state cycles, Setup cycles, or cycles where PWRITE=1.
Pass the sampled PRDATA value back to the system bus (AXI RDATA, AHB HRDATA) after the transfer completes.

PRDATA from multiple peripherals shares the same bus wires. The APB bridge only drives PSELx for one peripheral at a time. All other peripherals must drive their PRDATA to zero (or leave it tri-state if wired-OR is used) when their PSELx is deasserted. The recommended behaviour is to drive PRDATA=0 when PSELx=0. This prevents bus contention and makes logic analyser traces easier to read.

📋 Signal Stability During Reads

The signal stability rules for reads are almost identical to writes. The Requester-driven signals follow the same rules — they must be stable from Setup through completion. Only PRDATA (the Completer-driven read data) has different requirements.

Signal	Direction	Must be stable from	Until	Read-specific notes
`PADDR`	Req → Comp	Start of Setup	Transfer completes	Same as write — must not change during wait states
`PWRITE`	Req → Comp	Start of Setup	Transfer completes	Must be LOW (0) for entire read transfer
`PSELx`	Req → Comp	Start of Setup	Transfer completes	Same as write
`PENABLE`	Req → Comp	Start of Access	Transfer completes	Same as write
`PSTRB`	Req → Comp	Start of Setup	Transfer completes	Must be all-zero for reads. PSTRB has no meaning on a read but must be driven low.
`PPROT`	Req → Comp	Start of Setup	Transfer completes	Same as write — applies to reads too for secure/non-secure access control
`PRDATA`	Comp → Req	Before completion edge (setup time)	After completion edge (hold time)	Only valid at completion. Undefined during wait states.
`PWDATA`	Req → Comp	N/A	N/A	Not required to be valid during reads — but spec recommends driving to zero.

📋 Back-to-Back Read Transfers

Back-to-back reads work identically to back-to-back writes. PSELx stays asserted, PENABLE is deasserted for exactly one cycle (the Setup phase of the next read), then reasserted for the next Access phase.

Figure 4 — Back-to-back reads. PRDATA carries Data 1 at T2 (sampled by Requester). During Setup 2 (T3) PRDATA is undefined — the peripheral is fetching Data 2. At T4 (Access 2) PRDATA carries Data 2 and is sampled again.

📋 Mixed Read/Write Transfers

APB does not support concurrent reads and writes, but the bridge can perform reads and writes in any order — each one a separate sequential transfer. The direction (PWRITE) can change between transfers but never during a transfer.

Read-Modify-Write sequences are common. A typical peripheral access pattern is: (1) read a control register, (2) modify some bits in the bridge’s holding register, (3) write the modified value back. APB handles this as two sequential transfers — one read and one write — with an IDLE cycle between them unless back-to-back to the same peripheral.

Scenario	PWRITE value	PWDATA required?	PRDATA required?
Write transfer	1 (HIGH)	Yes — must be valid from Setup through completion	No — Completer does not drive PRDATA
Read transfer	0 (LOW)	No — spec recommends driving to 0	Yes — Completer drives valid data at completion
Idle (no transfer)	Don’t care	Don’t care	Completer should drive 0 when PSELx=0

📋 Quick Reference

Item	Rule
PWRITE value for read	0 (LOW) — must be stable throughout transfer
PSTRB during read	Must be all-zero — no byte-lane enable concept on reads
PWDATA during read	Not required to be valid — recommended to drive zero
PRDATA must be valid	At the rising PCLK edge where PSELx=1, PENABLE=1, PREADY=1, PWRITE=0
PRDATA during wait states	Undefined — Completer is preparing the value
PRDATA when PSELx=0	Should be driven to zero (recommended, not required)
Requester samples PRDATA at	Rising PCLK edge where PSEL+PENABLE+PREADY=1 and PWRITE=0
Minimum read duration	2 cycles — one Setup + one Access with PREADY=1
PRDATA bus contention	Only one peripheral drives PRDATA at a time — selected by PSELx. Others drive 0.
Difference from write	PWRITE=0, PRDATA driven by Completer instead of PWDATA, PSTRB must be 0
Back-to-back reads	PSELx stays HIGH, PENABLE deasserted for 1 cycle (new Setup), PRDATA undefined during that cycle
Read-Modify-Write	Two sequential transfers: read then write. IDLE between unless same peripheral.