🗺️ The journey, unit by unit
DE-01 · DE-02
Unit 1 — Number Systems & Codes
You started with the alphabet of digital systems — how numbers are represented in binary, octal, and hex; how 2’s complement makes subtraction an addition problem; and how encoding schemes like BCD, Gray code, and Hamming turn data into error-detectable bit patterns. Every datasheet you’ll ever read starts here.
DE-03 · DE-04
Unit 2 — Boolean Logic & Simplification
Huntington’s postulates, De Morgan’s theorems, SOP and POS forms, and then the real skill: K-map minimisation — the manual version of what every logic synthesiser does to your RTL. You learned to spot prime implicants, handle don’t-cares, and implement minimised circuits using only NAND or NOR gates. Quine-McCluskey showed you the algorithmic path for when K-maps get too large.
DE-05 · DE-06
Unit 3 — Combinational Circuits
Arithmetic circuits: the ripple of a half adder became a full adder, which became a parallel binary adder — the core of every ALU. BCD and XS-3 adders showed how decimal arithmetic maps to hardware. Then the catalogue of combinational building blocks: MUXes as function generators, decoders as minterm engines, priority encoders, magnitude comparators, parity checkers, and programmable logic (FPLA, PAL, PROM) showing how all of combinational logic can collapse into a single programmable array.
DE-07
Unit 4 — Logic Families
The electronics behind every gate symbol — from the historical arc of RTL and DTL through the TTL era (multi-emitter transistors, totem-pole outputs, open-collector wired-AND, tri-state buses) to ECL’s non-saturating differential amplifier giving 1 ns gates, and finally CMOS’s complementary transistor pairs that made near-zero static power possible. This unit explains why every modern VLSI chip is CMOS, and what that means for power, noise margin, and fan-out.
DE-08 · DE-09 · DE-10
Unit 5 — Sequential Circuits
Memory enters the picture. RS latches and their race conditions led to clocked flip-flops, and then the full flip-flop family — D, JK, T, Master-Slave — each solving the previous one’s limitation. Excitation tables and flip-flop conversion showed how any FF can be built from any other. Shift registers put FFs in series for serial-to-parallel conversion, time delay, and sequence generation. Counters put them in loops — asynchronous (with ripple glitches) and synchronous (with combinational carry logic), culminating in the 5-step synchronous counter design procedure and why Gray code counters matter for CDC FIFOs in real SoCs.
DE-11 · DE-12
Unit 6 — Mixed-Signal & Memory
The bridge between analog and digital. DACs built from weighted resistors and R-2R ladders (the VLSI-friendly one) convert binary codes to analog voltages. ADCs — Flash for speed, SAR for the sweet spot, dual-slope for precision — go the other direction. Then memories: the ROM family (mask, PROM, EPROM, EEPROM, Flash) for non-volatile storage; SRAM’s 6T cross-coupled latch for cache; DRAM’s one-transistor-one-capacitor cell for density — and why DRAM needs refresh while SRAM doesn’t. The memory hierarchy diagram tied all of it together: from flip-flop register files at the top to magnetic disk and optical storage at the bottom.
🔬 The VLSI connections you made
This series wasn’t just Digital Electronics theory — it was Digital Electronics as the foundation of VLSI. Here are the threads that ran through everything:
- K-map minimisation → logic synthesis — what Synopsys Design Compiler and Cadence Genus do to your RTL, every compile
- CMOS inverter pair → every standard cell — every gate in your standard cell library is a CMOS circuit using exactly the complementary topology from DE-07
- Setup/hold time → STA — the flip-flop timing parameters from DE-08 are the quantities Static Timing Analysis reports and flags as violations
- Gray code counters → CDC FIFOs — the only safe way to pass a pointer across a clock domain boundary without metastability
- 6T SRAM → cache design — the dominant area consumer in every modern processor die; process scaling makes write-ability and read stability increasingly difficult to balance
- SAR ADC → mixed-signal SoC — the architecture inside almost every on-chip ADC in every MCU, IoT chip, and sensor SoC ever made
- R-2R DAC → CMOS matched resistors — only two resistor values needed, and they track PVT variation together in silicon
- Floating-gate EPROM → embedded Flash — the same physics (trapped charge on a floating gate) powers every MCU’s program storage and every NAND Flash SSD
🚀 Where to go next
You’ve covered the hardware foundations. Here’s where this knowledge naturally leads:
Next Step
RTL Design with Verilog / SystemVerilog
Write synthesisable hardware descriptions of everything you just studied — counters, shift registers, FSMs, arithmetic units. Check out the SystemVerilog Series on VLSI Trainers.
Timing
Static Timing Analysis
Put numbers on the flip-flop setup/hold constraints from DE-08. STA calculates the longest path delay in your design and tells you whether your clock can run fast enough.
Verification
Functional Verification
Verify that RTL implementations of counters, decoders, and state machines actually behave as the truth tables in this series say they should.
Physical Design
VLSI Physical Design
Place the standard cells (built from the CMOS logic you now understand) and route the metal wires between them. The memory hierarchy from DE-12 maps directly onto floorplanning decisions.
Keep the Quick Reference tables. Every article ends with one. Bookmark or print those pages — they’re the fastest way to revise before a technical interview or exam. The flip-flop excitation tables, ADC comparison table, ROM family table, and counter IC table in particular come up constantly.
📝 Test what you know
Finished reading isn’t the same as knowing. Work through the question bank — it covers all 6 units with a mix of problem-solving questions, truth table completion, worked numerical examples, and short-answer conceptual questions.
Interview prep tip. The most commonly tested DE topics in VLSI/semiconductor interviews are: 2’s complement arithmetic, K-map minimisation of 4-variable functions, JK and D flip-flop behaviour, synchronous vs asynchronous counter differences, SRAM vs DRAM trade-offs, and DAC resolution calculations. All six are in the question bank.