128b/130b Encoding (Gen 3+)

📋 Why 8b/10b Was Replaced

Gen 3 was the first PCIe generation to double bandwidth without doubling frequency. Gen 1 ran at 2.5 GT/s, Gen 2 at 5 GT/s. Simply doubling to 10 GT/s for Gen 3 was considered impractical — the signal conditioning required at 5 GHz Nyquist frequency would demand expensive board materials and aggressive equalization that would price PCIe out of mainstream use.

The solution came from a different direction: keep the frequency increase modest (5 GT/s to 8 GT/s is only 60% more) and reclaim the 20% overhead that 8b/10b encoding had been wasting. The result is Gen 3 at 8 GT/s with ~98.5% efficiency — delivering approximately the same useful throughput as a hypothetical 10 GT/s system with 8b/10b.

Three specific problems with simply doubling frequency drove this decision: higher frequencies require far more expensive PCB laminate materials due to dielectric loss; signal conditioning logic (equalization) at 5 GHz+ is complex and power-hungry; and the existing PCIe connector and board infrastructure designed for 5 GT/s would have needed complete redesign for 10 GT/s signals.

📋 The Bandwidth Maths

The arithmetic behind 128b/130b is simple but important to understand precisely:

📋 128b/130b Block Structure

128b/130b groups 128 bits (16 bytes) of data into a single block and prepends a 2-bit sync header. This gives 130 bits on the wire for every 128 bits of payload — hence the name. Unlike 8b/10b which operates symbol-by-symbol, 128b/130b operates block-by-block.

The block boundary is fundamental to how Gen 3 framing works. Unlike 8b/10b where any K-code can appear between data characters, 128b/130b has no K-codes in the middle of data. Instead, the block structure defines what kind of content is present. A receiver must first achieve block alignment — knowing exactly where each 130-bit block starts in the serial bitstream — before it can interpret any data.

📋 The 2-bit Sync Header

The sync header is always exactly 2 bits, transmitted first in the block. Only two values are defined:

📋 Block Types — Data vs Ordered Set

The sync header divides blocks into two categories with fundamentally different behaviour:

📋 Framing Tokens in Data Blocks

In 8b/10b, K-codes (STP, SDP, END, EDB) are control characters that mark packet boundaries. In 128b/130b there are no K-codes — framing is done instead by special Framing Tokens embedded within data blocks. These tokens are specific byte patterns that the receiver recognises within the 128-bit payload of a data block.

STP token — the key improvement over 8b/10b STP

In 8b/10b, the TLP framing was: STP K-code at start, END K-code at end. The receiver had to wait to see the END to know where the TLP finished. In 128b/130b the STP token includes the TLP’s complete DW count as an 11-bit length field. The receiver can calculate exactly where the TLP ends from the moment it sees the STP. This enables faster cut-through forwarding at switches and simpler receiver logic.

The STP length field also has a 4-bit Frame CRC and an additional parity bit to protect against errors in the length itself — an error in the length field would cause the receiver to misalign on all subsequent packet boundaries until recovery. The triple-bit-flip detection capability of this combined protection makes the length field very robust.

📋 No K-Codes — What Replaced Each One

Every K-code from 8b/10b that had a function in PCIe Gen 1/2 is replaced in Gen 3 by either a framing token or an ordered set mechanism:

📋 Gen 3 Scrambler — Why Mandatory

In 8b/10b, scrambling was optional (a bit in the training sequence could disable it). In Gen 3, scrambling is mandatory and cannot be disabled. This is because 128b/130b encoding no longer guarantees transition density or DC balance by itself — it only provides the 2-bit sync header. The scrambler is the only mechanism that prevents long runs of the same bit value in the 128-bit payload, ensures sufficient transitions for CDR (Clock and Data Recovery), and maintains DC balance across the link.

📋 Scrambler LFSR Details

The Gen 3 scrambler uses a 23-bit Linear Feedback Shift Register (LFSR), significantly more complex than the 16-bit LFSR used in Gen 1/2. The generator polynomial is x²³ + x¹⁸ + 1. Each lane has its own independent LFSR, seeded with a different initial value per lane — this ensures that even if all lanes carry identical data bytes, the scrambled bitstreams on adjacent lanes are different, preventing crosstalk from becoming coherent.

📋 Block Alignment at the Receiver

Before a Gen 3 receiver can decode any data, it must achieve block alignment — determining exactly which bit in the incoming serial stream is the first bit of each 130-bit block. This replaces the symbol lock that 8b/10b achieved using the COM character’s unique pattern.

The procedure for achieving block alignment:

1. The receiver tentatively picks a starting bit position and looks at the first 2 bits as the sync header. It checks whether the value is 01 or 10 (valid) or 00 or 11 (invalid).
2. If valid, it jumps 130 bits forward and checks the next 2-bit sync header. If that is also valid, it repeats several more times.
3. After seeing a sufficient number of consecutive valid sync headers at the expected 130-bit intervals, the receiver declares block alignment achieved.
4. If at any point an invalid sync header appears (00 or 11), the receiver tries the next bit position and starts over.
5. The EIEOS ordered set (received as a sync=10 block with a specific all-ones-then-all-zeros pattern) provides a reliable reference point because it is unscrambled and has a well-known pattern.

📋 Lane-to-Lane Deskew in Gen 3

On a multi-lane link, the parallel bitstreams on different lanes travel slightly different path lengths and through slightly different electrical characteristics. They arrive at the receiver at slightly different times — lane-to-lane skew. The receiver must re-align all lanes before reassembling the packet byte stream.

In 8b/10b, the COM K-code served as the deskew reference — it appeared on all lanes simultaneously. In Gen 3, COM no longer exists. Deskew is performed using ordered set blocks, which must be transmitted simultaneously on all lanes. Any ordered set can serve as the deskew marker, but SKIP (SOS), SDS (Start Data Stream), and EIEOS are most commonly used because they appear regularly.

📋 SKIP Ordered Set for Clock Compensation

Clock tolerance compensation still works in Gen 3 via SKIP ordered sets (SOS), but the mechanism differs from 8b/10b. In Gen 1/2, the transmitter could insert SKP K-codes at fairly fine granularity within the bitstream. In Gen 3, insertion and deletion happen at block boundaries in multiples of 4 SKP symbols (bytes) per SOS.

• The transmitter sends an SOS every 370–375 blocks (each block being 130 bits). At 8 GT/s this is approximately every 6000 UI.
• The SOS is an ordered set block (sync=10) containing 16 bytes of SKIP content. The receiver may add or remove 4 SKP bytes from the SOS to adjust its elastic buffer level.
• Two consecutive SOS blocks are not allowed at Gen 3 — they must be separated by at least one data block.
• If a large TLP is in progress when an SOS is scheduled, the SOS transmission is deferred to the next packet boundary. Receivers must tolerate SOS separations up to: 375 blocks + (maximum packet size / 16 bytes per block) blocks.

📋 Gen 4 and Gen 5 Extensions

Gen 4 (16 GT/s) and Gen 5 (32 GT/s) both continue to use 128b/130b encoding. The block structure, sync header values, data/ordered set distinction, framing tokens, and scrambler mechanism are all carried forward unchanged. What changes generation-to-generation is the raw bit rate and the equalization requirements.

For Gen 4 and Gen 5, the encoding overhead and block structure are identical to Gen 3. The equalization training (Recovery.Equalization state in the LTSSM) runs more iterations with a larger coefficient search space, and the physical channel requirements become tighter — lower-loss laminates, tighter impedance control, and more aggressive equalization are all needed.

⚡ Gen 6 — Beyond 128b/130b

Gen 6 does not use 128b/130b encoding. The switch to PAM4 modulation at 32 Gbaud creates challenges that 128b/130b was not designed to handle. Instead, Gen 6 uses a completely different approach: flit-based framing with mandatory FEC.

Why 128b/130b could not scale to Gen 6

PAM4’s reduced eye opening means bit errors occur far more frequently than with NRZ. At 10⁻⁶ raw BER, a Gen 6 x16 link would have roughly one uncorrected bit error every microsecond without FEC — each requiring an ACK/NAK replay that consumes far more bandwidth than the original error saved. 128b/130b has no error correction — it can detect a bad sync header but cannot fix it. FEC is the only practical solution at PAM4 error rates.

Additionally, 128b/130b’s 130-bit block size is too fine-grained for efficient FEC coding. RS(544,514) operates on 256-byte (2048-bit) codewords — more than 15 times larger than a 130-bit block. Flit-based framing was designed specifically to match the FEC block size, giving the RS code enough data to correct multiple symbol errors per block efficiently.

📋 Quick Reference