Digital Memories – Your VLSI Journey Starts Here

🏗️ Memory Hierarchy & VLSI Context

Digital memories form a hierarchy — faster memories are smaller and more expensive; slower memories are larger and cheaper. Every VLSI SoC implements multiple levels of this hierarchy on a single die or in a package.

Figure 1 — Memory hierarchy pyramid. Moving down: access time increases, capacity increases, cost-per-bit decreases. The legend row shows which levels a modern VLSI SoC integrates on-chip — register files (flip-flops), SRAM caches (6T cells), embedded DRAM or Flash. Off-chip DDR DRAM and storage (SSD/HDD) fill the lower levels.

🔬 VLSI memory perspective. Memory accounts for over 60% of the area in most modern SoCs. Key on-chip memory types:

Register file — multi-port SRAM array holding the CPU’s architectural registers; critical path in processor design
SRAM caches — L1 (8–64 KB, <1 ns), L2 (256 KB–4 MB, ~5 ns); 6T SRAM cell; dominant area consumer
Embedded Flash — boot ROM, firmware storage in MCUs; EEPROM-based floating-gate cells
eDRAM — embedded DRAM stacked or on-die for bandwidth-intensive applications (GPU frame buffer, HBM)
ROM/LUT — look-up tables in FPGAs are implemented as small SRAMs; coefficient storage in DSPs uses ROM

📐 Memory Parameters

These six terms define how a memory unit behaves and are used on every datasheet:

Parameter	Definition	Typical values
Access time	Time from READ signal initiation to valid data available at output (tACC)	SRAM: 5–50 ns \| DRAM: 40–100 ns \| Flash: 50–100 µs
Write time	Time from WRITE signal initiation to data stably stored	SRAM: similar to access time \| EEPROM: 1–10 ms per byte
Memory cycle time	Minimum time between two successive memory operations. For destructive-readout memories: read time + restore write time	DRAM: 60–70 ns (row cycle) \| SRAM: equal to access time
Volatile vs non-volatile	Volatile: data lost when power removed (SRAM, DRAM). Non-volatile: data retained without power (ROM, Flash, magnetic disk)	RAM = volatile; ROM/Flash/magnetic = non-volatile
Destructive readout	Reading destroys stored data — must rewrite immediately after read. Magnetic core memories exhibit this; DRAM reading discharges the cell capacitor (also destructive)	Magnetic core, DRAM: destructive \| SRAM, ROM: non-destructive
Memory capacity	Total bits storable. Expressed as Words × Bits/word. 1 K = 2¹⁰ = 1024; 1 M = 2²⁰; 1 G = 2³⁰	MAR size n: memory has 2ⁿ words. MBR size k: word length k bits.

📬 MAR, MBR, and Capacity Calculations

Every memory system has two key registers:

MAR (Memory Address Register) — holds the address of the location being read or written. If the memory has 2ⁿ locations, MAR needs n bits.
MBR (Memory Buffer Register) — holds the data being read from or written to memory. Its width equals the word length in bits.

Example 12.1 — 16K × 32 memory: find MAR and MBR sizes

MBRWord length = 32 bits → MBR = 32 bits

MAR16K words = 16 × 1024 = 2¹⁴ locations → MAR = 14 bits

MAR = 14 bits MBR = 32 bits

Example 12.2 — 8K × 20 memory: capacity and register sizes

Words8K = 8 × 1024 = 8192 words

Total bits8192 × 20 = 163,840 bits

MBRWord length = 20 bits → MBR = 20 bits

MAR2¹³ = 8192 → MAR = 13 bits

8192 words, 163,840 bits total MAR = 13 bits MBR = 20 bits

Address space formula: For n MAR bits → 2ⁿ addressable locations. A 32-bit processor has a 32-bit MAR → 2³² = 4 GB address space. A 64-bit processor can address 2⁶⁴ bytes (18 exabytes) theoretically, though practical systems implement only 48–52 bits.

💿 ROM — Read Only Memory

A ROM stores data permanently at manufacture time. It can be read but not written. The data is encoded in a 2D array (matrix) — the presence or absence of a transistor/diode at each intersection encodes a 1 or 0.

Figure 2 — 8×5 diode matrix ROM. The 3-to-8 decoder selects one row based on address A₂A₁A₀. Diodes on the selected row conduct, pulling the corresponding column lines HIGH (logic 1). Columns with no diode remain LOW (logic 0). The 5-bit pattern appears on b₄–b₀.

ROM Cell Technologies

Technology	Cell for bit=1	Cell for bit=0	Speed	Density
Diode matrix	Diode at intersection	No diode	Slow	Low
Bipolar (BJT)	Transistor: base→row, emitter→column	Base disconnected (open)	Fast	Medium
MOS (NMOS/CMOS)	MOSFET: gate→row, source→column	Gate disconnected (floating)	Medium	High

🔥 PROM — Programmable ROM

A PROM is manufactured with all fuses intact (all bits = 1). The user programs it once by blowing selected fuses using a PROM programmer — high current pulses through the emitter fuse burn it open, storing a 0 at that cell. Once a fuse is blown it cannot be restored.

Write: Once only — one-time programmable (OTP)
Erase: Not possible — permanent
Technology: Bipolar (fast) or MOS
Use case: Field-programmable code storage, firmware that never changes, security keys

Programming rule: Unprogrammed bit = 1 (fuse intact). Programmed bit = 0 (fuse blown). You can set bits from 1→0 but never 0→1. Plan the full data pattern before programming — there are no second chances.

☀️ EPROM — Erasable PROM (UV Light)

Each EPROM cell is a floating-gate MOSFET. The floating gate is completely surrounded by silicon dioxide insulator. Programming injects high-energy electrons onto the floating gate using a high-voltage (12–25V) programming pulse — stored charge keeps the transistor permanently ON (bit = 0). Unprogrammed cells store bit = 1.

Figure 3 — EPROM cell operation. The floating gate retains charge because it is completely surrounded by SiO₂ insulator — there is no DC path for charge to leak. UV erasing takes 25–30 minutes for the entire chip; cover the quartz window with opaque tape after programming to protect from accidental erasure.

27xx EPROM Series

Part number	Capacity	Address lines	Word size
2716	2K × 8 = 16 Kbit	11	8-bit
2732	4K × 8 = 32 Kbit	12	8-bit
2764	8K × 8 = 64 Kbit	13	8-bit
27128	16K × 8 = 128 Kbit	14	8-bit
27256	32K × 8 = 256 Kbit	15	8-bit

⚡ EEPROM — Electrically Erasable PROM

EEPROM (E²PROM) uses the same floating-gate MOS cell as EPROM but adds a very thin oxide region above the drain. This thin oxide (Fowler-Nordheim tunneling oxide) allows electrons to tunnel onto or off the floating gate electrically — no UV light needed.

Feature	EPROM	EEPROM
Erase method	UV light, 25–30 min	Electrical (~21V pulse), 10 ms
Erase granularity	Entire chip only	Individual byte or word
In-circuit programmable	No — requires removal	Yes — reprogram in circuit
Quartz window	Required	Not needed
Endurance	~100 erase cycles	10,000–1,000,000 cycles
Cell size	Smaller (1T)	Slightly larger (thin-oxide MOSFET)

🔬 Flash memory — the EEPROM successor. Modern Flash memory is a mass-market evolution of EEPROM — NOR Flash (byte-addressable, fast read, used for code storage) and NAND Flash (block-erase, high density, used for data storage — SD cards, SSDs, eMMC). Flash erase is in blocks (typically 128 KB–4 MB), writes are byte/page-programmable. Floating-gate and charge-trap (CTF) cell designs are both used in production Flash. All modern MCUs integrate NOR Flash for on-chip program storage.

🛠️ ROM Applications

Logic Function Implementation

Look-up Tables (LUTs)

Code Converters

Character Generators

Waveform / Function Generators

Logic Function Implementation

Any Boolean function of n variables can be implemented directly in a 2ⁿ-word ROM. The n input variables are the address lines. The data stored at each address is the function output for that minterm. Multiple output functions (f₁, f₂, f₃…) share the same ROM — each uses one output data bit.

Example 12.3 — Four functions of 5 variables using 32×8 PROM

PROM size32 × 8 = 32 addresses (5 address bits) × 8 data bits

Assignf₁→b₀, f₂→b₁, f₃→b₂, f₄→b₃. Remaining bits b₄–b₇ left open (don’t care).

ProgramFor each address 0–31: set bₓ=1 if address is a minterm of fₓ, else bₓ=0.

One 32×8 PROM replaces 4 separate combinational logic networks — no K-map minimisation needed.

Look-up Tables

A 128×8 ROM implements sin(x): 7 address bits represent the angle in 1.4° steps (0–178.6°), and the 8 data bits represent the sine value scaled to 0–255. The processor looks up the precomputed value in one ROM read cycle — far faster than computing sin(x) in software.

Character Generators

A 5×7 dot-matrix character generator ROM stores the ON/OFF pattern of 35 dots for each ASCII character. Address = ASCII code; each row read gives 5 bits (one dot-row of the character). Used in early video terminals and alphanumeric displays.

Waveform / Function Generator

A ROM storing 256 samples of one sine wave cycle, addressed by an 8-bit counter, drives a DAC to produce a continuous analog sine wave. Frequency = f_CLK / 256. Change f_CLK to change the output frequency. This is the basis of Direct Digital Synthesis (DDS) — used in signal generators and software-defined radio.

Code Converter with ROM. Binary→Gray: 4 address lines (binary input), 4 data outputs (Gray code). Populate 16 locations with the Gray code equivalents. One ROM read converts a 4-bit binary number to Gray code — no XOR gates needed. Similarly any code conversion (BCD→Excess-3, ASCII→EBCDIC) maps directly to a ROM.

🔄 RAM — Random Access Memory

RAM supports both read and write in equal access time. “Random access” means any location can be accessed directly in constant time — unlike sequential-access memories (tape, disk) where access time depends on current head position.

Linear Selection vs Coincident (X-Y) Selection

Figure 4 — Selection methods. Coincident selection exponentially reduces the number of decoder lines needed for large memories. DRAM RAS/CAS strobes directly implement coincident selection — multiplexing row and column addresses on the same pins to halve address pin count.

🔒 SRAM — Static MOS RAM Cell (6T)

The standard SRAM cell is a cross-coupled CMOS inverter pair (4 transistors: Q1–Q4) plus two access transistors (Q5, Q6) controlled by the word line (WL). Data is held statically as long as power is supplied — no refresh needed.

Figure 5 — 6T SRAM cell. Q3+Q1 and Q4+Q2 form cross-coupled CMOS inverters (a latch). Q5 and Q6 are access transistors controlled by the Word Line (WL). When WL is HIGH, Q5 and Q6 connect the internal latch to the bit lines (BL, BL̄) for read or write. The latch retains state indefinitely as long as power is applied.

🔬 SRAM in VLSI design. The 6T SRAM cell is the most area-critical element in processor design. A typical L1 cache of 32 KB contains ~2.6 million transistors just for storage — before sense amplifiers, decoders, and column multiplexers. Key VLSI concerns: cell stability (noise margin during read, write-ability), leakage in standby, bit-line capacitance, sense amplifier offset. Process scaling below 10nm requires assist circuits (negative bit-line, word-line boosting) to maintain read/write margins.

⚡ DRAM — Dynamic MOS RAM Cell (1T1C)

The DRAM cell uses just one transistor and one capacitor — far smaller than the 6T SRAM cell, enabling much higher density (Gb/chip vs Mb/chip). Data is stored as charge on the capacitor. The transistor acts as an access switch.

Operation	Address line	Bit/sense line	Capacitor
Write 1	HIGH (transistor ON)	HIGH voltage	Charges to V_DD (stores 1)
Write 0	HIGH (transistor ON)	LOW (0V)	Discharges to 0V (stores 0)
Read	HIGH (transistor ON)	Sense amplifier detects	Charge shared with bit line → destructive
Refresh	Rows refreshed cyclically	Sense amp restores charge	Required every 32–64 ms

Why DRAM needs refresh. The storage capacitor (typically 10–30 fF) has a finite leakage resistance. Charge bleeds away in ~50–100 ms. The DRAM controller must read (and rewrite) every row within the refresh interval — typically every 64 ms, cycling through all rows. Modern DDR5 DRAMs perform this automatically (on-die ECC and refresh management), but the fundamental 1T1C physics hasn’t changed since the 1970s.

🔬 DRAM vs SRAM in VLSI. SRAM: fast (5 ns), no refresh, 6T cell — used for on-chip caches. DRAM: slow (~50 ns), needs refresh, 1T1C cell — used for main memory (GB-scale). Modern trends: High Bandwidth Memory (HBM) stacks multiple DRAM dies on a silicon interposer next to the processor using through-silicon vias (TSVs), reducing the memory bandwidth bottleneck. Embedded DRAM (eDRAM) integrates DRAM directly on the processor die for L3/L4 cache (IBM Power, Intel processors).

🔌 RAM ICs

IC 7489 — 16×4 Bipolar RAM

A simple 16-word × 4-bit bipolar RAM. Inputs: 4-bit address (select), Memory Enable (M̄Ē, active-low), Write Enable (W̄Ē, active-low). Output: 4-bit data (complemented — low output = stored 1). Useful for small fast lookup tables in SSI/MSI designs.

IC 2147 — 4K×1 Static NMOS RAM

A 4096-word × 1-bit SRAM. Separate Data In and Data Out pins. Chip Select (C̄S̄, active-low) activates the chip. Write Enable (W̄Ē, active-low) for write; C̄S̄ alone for read. Cascade 8 ICs for 4K×8 = 32 Kbit word-wide RAM.

IC 4164 — 64K×1 Dynamic NMOS RAM

A 65,536-word × 1-bit DRAM. The 16-bit address is multiplexed over 8 address pins using RAS (Row Address Strobe) and CAS (Column Address Strobe). The memory is organised as a 256×256 matrix — 8 RAS bits address 256 rows, 8 CAS bits address 256 columns.

Parameter	IC 7489	IC 2147	IC 4164
Type	Bipolar RAM	SRAM (NMOS)	DRAM (NMOS)
Capacity	16 × 4 bits	4K × 1 bit	64K × 1 bit
Address pins	4	12	8 (multiplexed)
Address method	Linear	Linear	RAS/CAS (coincident)
Refresh needed	No	No	Yes (~2 ms)
Access time	~35 ns	~55 ns	~120–200 ns
Output	Complemented	Non-inverting	Non-inverting

📦 Expanding RAM — Word-Width and Address Space

Increasing Word Width (Parallel Connection)

Connect multiple RAM ICs in parallel, sharing the same address and control lines, but each contributing its own data bits. Two 7489 (16×4) ICs connected in parallel = 16×8 RAM — the address lines of both ICs are tied together; one IC provides bits b₇–b₄, the other provides b₃–b₀.

Increasing Address Space (Series Connection with Decoder)

To expand the number of addressable words, use a decoder driven by the extra address bits to select which IC’s Chip Select is active. Example: four 1K×8 PROMs + 2-to-4 decoder = 4K×8 ROM. Each PROM handles 1K addresses; the 2-bit MSB selects which PROM is active via the decoder’s output connecting to each IC’s Chip Enable (C̄Ē).

Build 4K×8 memory from 1K×8 PROMs

Need4K = 4096 words × 8 bits = 4K×8. Each PROM: 1K×8.

Count4K / 1K = 4 PROMs required

Address1K×8 PROM has 10 address lines (A₉–A₀). 4K needs 12 lines (A₁₁–A₀). Use A₁₁–A₁₀ as chip-select decoder inputs.

Decoder2-to-4 decoder driven by A₁₁,A₁₀ → outputs Y₀–Y₃ each connected to C̄Ē of one PROM

A₁₁A₁₀ = 00 → PROM 0 active (addr 0–1023); 01 → PROM 1 (1024–2047); 10 → PROM 2; 11 → PROM 3

💾 Magnetic Memories

Magnetic Core Memory

A toroidal ferrite core stores one bit as the direction of magnetic flux (clockwise = 0, counter-clockwise = 1). The hysteresis curve is nearly rectangular — the core snaps between ±Φ_m with no intermediate states. Reading is destructive — the read current drives the core to −Φ_m to sense the change; a rewrite must follow immediately. Used in mainframes through the 1970s. Non-volatile (data survives power-off).

Magnetic Disk — Data Encoding Standards

RZ (Return to Zero)

Pulse for ‘1’, no pulse for ‘0’. Signal always returns to 0 after each ‘1’. Simple but wastes bandwidth.

NRZ (Non-Return to Zero)

High = ‘1’, low = ‘0’. No transition within a bit. Common for serial data, but no self-clocking.

Biphase

Always a mid-bit transition. ‘1’ = high→low at mid-bit; ‘0’ = low→high at mid-bit. Self-clocking.

Manchester

High→low at bit start = ‘0’; no transition = ‘1’. Used in Ethernet, RFID. Self-clocking, DC-balanced.

Kansas City

‘1’ = 8 cycles of 2.4 kHz; ‘0’ = 4 cycles of 1.2 kHz. Frequency-shift keying used in early cassette storage.

Floppy Disk

5.25-inch floppy: 77 tracks × 26 sectors × 128 bytes/sector = 256 KB total. The plastic jacket protects the flexible Mylar disk. The index hole provides the angular reference. A write-protect notch prevents accidental overwriting when covered with tape. Average access time ~500 ms — slow by modern standards but revolutionary in the 1970s–80s.

Hard Disk

Rigid aluminium platters coated with magnetic material, stacked on a rotating spindle at 3600–5400 RPM. The read/write heads float on an air cushion ~100 nm above the surface. Data transfer rates: 1–10 Mb/s (early HDD). Modern HDDs achieve 200–300 MB/s with 10+ TB capacity using perpendicular magnetic recording (PMR) and heat-assisted magnetic recording (HAMR).

💡 Bubble Memory, CCD, and CD-ROM

Magnetic Bubble Memory

Cylindrical magnetic domains (“bubbles”) in garnet material represent data — bubble present = 1, absent = 0. Bubbles are moved along predefined tracks by a rotating magnetic field (no mechanical motion). Capacity up to 1 Mb/chip. Non-volatile, solid-state, highly reliable — but slow access. Used in specialised industrial/military applications. Largely obsolete — superseded by Flash.

Charge Coupled Devices (CCD)

Data stored as charge packets in capacitor arrays. Charge shifts from cell to cell on each clock pulse — sequential access only (not random). Must be refreshed like DRAM. Used in imaging sensors (CCD cameras) rather than data storage today. Access time is not constant.

CD-ROM (Optical Memory)

650 MB capacity on a 120 mm polycarbonate disc coated with reflective aluminium. Data encoded as microscopic pits (≈ 0.83 µm diameter) and lands on a spiral track. Pits are created by a high-intensity laser on the master disc; copies stamped in bulk. Reading uses a low-power laser — a pit-to-land or land-to-pit transition = 1; no transition within a stretch = 0. Rotates at 360 RPM with constant linear velocity (CLV). Entirely read-only (hence ROM in the name).

CD-ROM → DVD → Blu-ray → NVMe SSD. The trend has been from optical (slow, large, mechanical) to Flash (fast, compact, no moving parts). Modern SSDs (NVMe PCIe Gen5) achieve 7+ GB/s sequential read — 7000× faster than a 1× CD-ROM drive. In VLSI systems, persistent storage is now Flash-based (NAND Flash in eMMC/UFS/NVMe), with the memory controller implemented as a dedicated SoC managing wear leveling, ECC, and FTL (Flash Translation Layer).

📋 Quick Reference

ROM Family Comparison

Type	Written by	Erasable	Reprogrammable	Technology
ROM (mask)	Manufacturer (mask)	No	No	Diode/BJT/MOS matrix
PROM	User (one time)	No (fuses blown)	No	Fusible link BJT/MOS
EPROM	User (programmer)	UV light (whole chip, 25 min)	Yes (after UV erase)	Floating-gate MOSFET
EEPROM	User (in circuit)	Electrical (byte/word, 10 ms)	Yes (10k–1M cycles)	Thin-oxide floating gate
Flash NOR	User (in circuit)	Electrical (sector, ~1 ms)	Yes (100k cycles)	Floating gate / CTF

RAM Comparison

Parameter	SRAM	DRAM
Cell	6T (cross-coupled inverters)	1T1C (transistor + capacitor)
Refresh	Not needed	Required every 64 ms
Access time	5–50 ns (fast)	40–100 ns (slower)
Density	Low (6 transistors/bit)	High (1 transistor + 1 capacitor/bit)
Power	Higher (static, no refresh)	Lower dynamic, refresh overhead
Readout	Non-destructive	Destructive (capacitor discharges)
Volatile	Yes	Yes
VLSI use	L1/L2 cache, register files	Main memory (off-chip DDR / HBM)

Memory Parameters Formula Sheet

Calculation	Formula
MAR width	n bits where 2ⁿ = number of words
MBR width	= word length in bits
Total bits	words × bits/word
1 K =	2¹⁰ = 1024 1 M = 2²⁰ 1 G = 2³⁰
27xx EPROM address lines	2716 = 2K×8 → 11 addr lines 2732 = 4K×8 → 12 lines

Series complete! This is the final article in the 12-part Digital Electronics series. You have now covered: Number Systems (DE-01) → Binary Codes (DE-02) → Boolean Algebra (DE-03) → K-Map Simplification (DE-04) → Arithmetic Circuits (DE-05) → Combinational Circuits (DE-06) → Logic Families (DE-07) → Flip-Flops (DE-08) → Shift Registers (DE-09) → Counters (DE-10) → DAC & ADC (DE-11) → Digital Memories (DE-12).

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