SISO, SIPO, PISO, PIPO — Bidirectional and Universal shift registers — Ring counter and Johnson counter — IC details (7491, 74164, 74194, 74195) — Serial adder, parity generator, time delay, data conversion, and sequence generator applications.
A register is a group of n flip-flops sharing a common clock, capable of storing an n-bit binary word. A single D flip-flop stores 1 bit — it transfers the D input to its output on the clock edge and holds that value until the next clock edge.
When flip-flops are connected so that the output of each feeds the input of the next — with each clock pulse shifting the stored pattern one position — the circuit is a shift register. Shift registers serve as temporary storage and also implement serial-to-parallel and parallel-to-serial data conversion.
Input: 1 bit per clock (serial). Output: all n bits simultaneously (parallel).
Data shifts in one bit at a time — after n clocks the full word is available on all Q outputs at once.
Use: Serial-to-parallel conversion, receiving serial data streams.
Input: 1 bit per clock. Output: 1 bit per clock, delayed by n clock periods.
The complete word must be shifted through all n stages to appear at Q₀. Acts as a digital time-delay line.
Use: Time delay, pipeline buffers, shift-register counters.
Input: all n bits simultaneously (parallel). Output: all n bits simultaneously.
A LOAD pulse latches all inputs into all flip-flops at once. Data is available immediately at all Q outputs.
Use: Data storage registers, CPU internal registers.
Input: all n bits in one LOAD clock. Output: 1 bit per subsequent clock.
WRITE/LOAD mode fills all flip-flops in one clock. SHIFT mode outputs bits one by one from the last FF.
Use: Parallel-to-serial conversion, SPI/UART transmission.
Four D flip-flops in series. The output of each stage’s Q feeds the D input of the next. All Q outputs are accessible simultaneously for parallel readout.
| Clock pulse | Input bit | Q₃ | Q₂ | Q₁ | Q₀ |
|---|---|---|---|---|---|
| Initial | — | 0 | 0 | 0 | 0 |
| 1↓ | 1 | 1 | 0 | 0 | 0 |
| 2↓ | 1 | 1 | 1 | 0 | 0 |
| 3↓ | 1 | 1 | 1 | 1 | 0 |
| 4↓ | 1 | 1 | 1 | 1 | 1 |
Identical hardware to SIPO — four D flip-flops in series — but only the last flip-flop’s output (Q₀) is used. To retrieve data, n additional clock pulses must be applied after loading, shifting bits out one at a time through Q₀. Total clocks needed = n (to load) + n (to unload) = 2n.
| Clock | Input | Q₃ | Q₂ | Q₁ | Q₀ (serial out) |
|---|---|---|---|---|---|
| Initial (CLR) | — | 0 | 0 | 0 | 0 |
| 1↓ | 1 (LSB) | 1 | 0 | 0 | 0 |
| 2↓ | 0 | 0 | 1 | 0 | 0 |
| 3↓ | 1 | 1 | 0 | 1 | 0 |
| 4↓ | 1 (MSB) | 1 | 1 | 0 | 1 ← LSB out |
| 5↓ | 0 | 0 | 1 | 1 | 0 |
| 6↓ | 0 | 0 | 0 | 1 | 1 |
| 7↓ | 0 | 0 | 0 | 0 | 1 ← MSB out |
All flip-flops share a LOAD/PARALLEL TRANSFER signal. When the LOAD signal is HIGH, all AND gates are enabled, connecting all data inputs D₃D₂D₁D₀ to their respective flip-flop D inputs simultaneously. On the next clock edge, all data is loaded at once and all Q outputs reflect the loaded data immediately.
The PISO register operates in two phases controlled by a WRITE/SHIFT̄ line:
| Clock | Mode | Q₃ | Q₂ | Q₁ | Q₀ (serial) |
|---|---|---|---|---|---|
| 1↑ | WRITE | 1 | 0 | 0 | 1 |
| 2↑ | SHIFT | 0 | 1 | 0 | 0 ← |
| 3↑ | SHIFT | 0 | 0 | 1 | 0 ← |
| 4↑ | SHIFT | 0 | 0 | 0 | 1 ← |
| 5↑ | SHIFT | 0 | 0 | 0 | 1 ← MSB |
A bidirectional (left/right) shift register uses NAND gates configured as OR selectors to connect each flip-flop’s D input to either the right or left adjacent flip-flop’s Q output, under control of the SHR/SHL̄ signal.
| SHR/SHL̄ | Operation | Effect on binary number |
|---|---|---|
| 1 (HIGH) | Shift RIGHT — Q of each FF → D of next FF to the right | Divide by 2 (arithmetic right shift) |
| 0 (LOW) | Shift LEFT — Q of each FF → D of preceding FF to the left | Multiply by 2 (arithmetic left shift) |
A universal shift register supports all four modes of operation plus bidirectional shifting, controlled by two mode-select inputs S₁ and S₀.
| S₁ | S₀ | Operating Mode | Description |
|---|---|---|---|
| 0 | 0 | No Change | Hold — register retains current contents |
| 0 | 1 | Shift Right | Serial data enters at shift-right input (SR); shifts right on each clock |
| 1 | 0 | Shift Left | Serial data enters at shift-left input (SL); shifts left on each clock |
| 1 | 1 | Parallel Load | Data D₃D₂D₁D₀ loaded simultaneously on next clock |
Key IC: 74194 4-bit bidirectional universal shift register. Positive edge triggered, synchronous parallel load, independent left/right shift with separate serial inputs, active-low asynchronous clear.
A ring counter is a SISO shift register with the output of the last flip-flop (Q₀) connected back to the input of the first. A single 1 circulates around the register indefinitely. An n-bit ring counter has n states and repeats every n clock pulses.
The Johnson counter differs from the ring counter by connecting the complement output Q̄ of the last flip-flop back to the D input of the first — the “twist.” This produces 2n states from n flip-flops (double the ring counter), and generates a sequence with only one bit changing at a time (like Gray code).
| Clock | Q₃ | Q₂ | Q₁ | Q₀ | State |
|---|---|---|---|---|---|
| 0 (reset) | 0 | 0 | 0 | 0 | 0 |
| 1 | 1 | 0 | 0 | 0 | 1 |
| 2 | 1 | 1 | 0 | 0 | 2 |
| 3 | 1 | 1 | 1 | 0 | 3 |
| 4 | 1 | 1 | 1 | 1 | 4 |
| 5 | 0 | 1 | 1 | 1 | 5 |
| 6 | 0 | 0 | 1 | 1 | 6 |
| 7 | 0 | 0 | 0 | 1 | 7 |
| 8→ | 0 | 0 | 0 | 0 | → back to 0 |
| Property | Ring Counter | Johnson Counter |
|---|---|---|
| n flip-flops → states | n states | 2n states |
| Feedback | Q of last FF → D of first | Q̄ of last FF → D of first |
| 4 FFs → modulus | MOD-4 | MOD-8 |
| Bits changing per step | 1 (single 1 moves) | 1 (Gray code-like) |
| Decode complexity | None (Q directly = state) | 2-input AND/NAND per state |
| IC No. | Type | Bits | Key Features |
|---|---|---|---|
| 7491 / 7491A | SISO | 8-bit | Two gated serial inputs A and B; QH and Q̄H outputs; enter through A with B=1 or B with A=1 |
| 7494 | PISO | 4-bit | Parallel-in, serial-out |
| 7495 | SIPO / PIPO | 4-bit | Serial or parallel in, parallel out; left/right shift |
| 74164 | SIPO | 8-bit | Two gated serial inputs A,B; 8 parallel outputs QA–QH; active-low CLR |
| 74165 | PISO | 8-bit | SH/LD̄ control; serial and parallel inputs; complementary outputs QH, Q̄H |
| 74194 | Universal (bidirectional) | 4-bit | S₁,S₀ mode select; separate SR and SL serial inputs; parallel I/O; synchronous clear; the most versatile shift register IC |
| 74195 | PISO (universal) | 4-bit | SH/LD̄ control; J-K serial input to first stage; parallel I/O; complementary QA and Q̄A |
| 74198 | Universal (bidirectional) | 8-bit | Extended 74194 to 8 bits |
Two shift registers (augend A and addend B) plus a full adder and carry flip-flop implement serial addition. Augend and addend bits are shifted out LSB-first on each clock — the full adder adds one bit pair per clock with carry from the previous stage. The sum bit re-enters register A. After n clocks the complete n-bit sum is in register A.
Advantage vs parallel adder: Only one full adder needed (saves hardware). Disadvantage: Requires n clock cycles vs single-cycle parallel addition.
A SISO register of N stages introduces a time delay of:
Δτ = N × T_CLK = N / f_CLK
Example: N=8 stages, f_CLK = 500 kHz → Δτ = 8 × 2μs = 16μs delay. Change N or f_CLK to control the delay precisely.
A shift register clocked at the bit rate, with XOR feedback, accumulates the running XOR of all data bits. After n clocks the stored bit is the even parity of all n input bits. The same circuit checks parity at the receiver — if the final XOR of data + received parity bit is non-zero, an error occurred.
Connect the parallel outputs of a SISO register to a combinational logic network whose output feeds the serial input. By designing the feedback combinational circuit appropriately, any desired repeating binary sequence can be generated. Used in spread-spectrum communications (LFSR), test pattern generation, and digital signal synthesis.
Required sequence has 6 bits → need N=3 stages (since 6 ≤ 2³=8). Feedback function derived from K-map:
| Type | Input | Output | Clocks to load | Key use |
|---|---|---|---|---|
| SIPO | Serial (1 bit/clk) | Parallel (all at once) | n | Serial → parallel conversion |
| SISO | Serial (1 bit/clk) | Serial (1 bit/clk, delayed) | n (load) + n (unload) | Time delay, pipeline |
| PIPO | Parallel (all at once) | Parallel (all at once) | 1 | Data storage registers |
| PISO | Parallel (1 clock) | Serial (1 bit/clk) | 1 (load) + n (shift) | Parallel → serial conversion |
| Counter type | n FFs → states | Modulus | Bits/step |
|---|---|---|---|
| Ring counter | n states | n | 1 (one 1 moves) |
| Johnson counter | 2n states | 2n | 1 (Gray-code-like) |
| IC | Type | Bits | Key pin |
|---|---|---|---|
| 7491 | SISO | 8 | Gated inputs A,B |
| 74164 | SIPO | 8 | Gated A,B; active-low CLR̄ |
| 74194 | Universal bidirectional | 4 | S₁S₀ mode; SR,SL serial inputs |
| 74195 | PISO (universal) | 4 | SH/LD̄; J-K serial input |