Multiplexers, Demultiplexers, Decoders (3-to-8, BCD-to-decimal, BCD-to-7-segment), Code Converters, Encoders, Priority Encoders, Magnitude Comparators, Parity Generator/Checker, and Programmable Logic Devices — FPLA, PAL, and PROM.
A multiplexer (MUX), also called a data selector, routes one of N data inputs to a single output line under the control of K select lines, where 2K = N. Only one input is connected to the output at a time.
74157 Quadruple 2:1 MUX (4 × two-input MUXes on one chip) 74151A 8:1 MUX — 8 data inputs, 3 select lines, active-low enable 74150 16:1 MUX — 16 inputs, 4 select lines
Larger MUXes are built by cascading smaller ones. Two 4:1 MUXes form an 8:1 MUX — a NOT gate on the most-significant select line S₂ drives the enable of each 4:1 MUX, giving a third effective select terminal. When S₂=0, the first MUX (inputs X₀–X₃) is enabled; when S₂=1, the second MUX (inputs X₄–X₇) is enabled. Their outputs connect to a common OR gate for the final output.
An N-input MUX can directly implement any Boolean function of log₂(N) variables — connect inputs to 0 or 1 per the truth table output column. With one fewer select line than variables, use the MSB as a variable-valued data input.
Connect the variables to the select lines. For each input Xᵢ: set Xᵢ = 1 if the truth table output is 1 at row i, else Xᵢ = 0.
Connect A, B, C to select lines S₂, S₁, S₀ respectively.
Use the MSB (A) as a data input. The other variables drive the select lines. For each pair of rows (A=0 and A=1 with same remaining variables), the data input Xᵢ is:
Use B,C,D as select lines S₂,S₁,S₀. MSB = A as data variable.
A demultiplexer is the reverse of a MUX — it routes a single data input to one of 2N output lines selected by N control bits. Also called a data distributor.
Key ICs: 74155 Dual 1:4 DEMUX (= 2:4 decoder) 74138 1:8 DEMUX (= 3:8 decoder) 74154 1:16 DEMUX (= 4:16 decoder)
A decoder accepts an N-bit binary input and asserts exactly one of 2N output lines — the one corresponding to the input value. All other outputs remain inactive.
| A | B | C | Enable E | Active output | Expression |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 1 | Y₀ | Ā·B̄·C̄ |
| 0 | 0 | 1 | 1 | Y₁ | Ā·B̄·C |
| 0 | 1 | 0 | 1 | Y₂ | Ā·B·C̄ |
| 0 | 1 | 1 | 1 | Y₃ | Ā·B·C |
| 1 | 0 | 0 | 1 | Y₄ | A·B̄·C̄ |
| 1 | 0 | 1 | 1 | Y₅ | A·B̄·C |
| 1 | 1 | 0 | 1 | Y₆ | A·B·C̄ |
| 1 | 1 | 1 | 1 | Y₇ | A·B·C |
| Any | 0 | None | All Y = 0 | ||
Each output Yᵢ of a decoder is exactly minterm mᵢ. To implement any SOP function, OR together the decoder outputs corresponding to the minterms in the function. One decoder can implement multiple functions simultaneously — much more economical than one MUX per function.
Connect the 4th input bit to the Enable of each 3-to-8 decoder through a NOT gate. When the MSB is 0, decoder 1 is enabled (covers outputs 0–7); when MSB is 1, decoder 2 is enabled (covers outputs 8–15).
Converts a 4-bit BCD input (0000–1001) to one of ten active output lines (0–9). Also called a 4-to-10 line decoder. The six illegal codes (1010–1111) produce no output.
Key IC: 74LS42 / 7442 — BCD-to-decimal decoder. Built with NAND gates → active-low outputs (selected output goes LOW, others stay HIGH). Used in numeric display driving and BCD demultiplexing.
Drives a 7-segment LED display from a 4-bit BCD input. The seven segments a–g are independently controlled by seven Boolean expressions, each derived from K-map minimisation of the display truth table.
| Segment | Minimal Boolean Expression | Segments lit for… |
|---|---|---|
| a | A + C + B·D + B̄·C̄ | 0,2,3,5,6,7,8,9 |
| b | B̄ + C·D + C̄·D̄ | 0,1,2,3,4,7,8,9 |
| c | B̄ + C̄ + D | 0,1,3,4,5,6,7,8,9 |
| d | A + B·D̄ + B̄·C̄ + B̄·C·D | 0,2,3,5,6,8 |
| e | B̄·D̄ + C·D̄ | 0,2,6,8 |
| f | A + C̄·D̄ + B·C̄ + B·D̄ | 0,4,5,6,8,9 |
| g | A + B·C̄ + B̄·C + C·D̄ | 2,3,4,5,6,8,9 |
Key ICs: 7447 BCD-to-7-seg decoder/driver (active-low outputs, 15V max) 7446 Same as 7447 but 30V max. Both provide Lamp Test (LT̄), Ripple Blank Input (RB̄Ī), and Ripple Blank Output (R̄B̄O) for leading-zero blanking in multi-digit displays.
A code converter transforms a binary word from one encoding to another — for example 8421 BCD to Gray code, or Gray to 8421. The method: build a truth table with the input code as input variables and the output code as output variables, then minimise each output bit’s expression using K-maps.
An encoder is the reverse of a decoder — it has 2N (or fewer) input lines, exactly one of which is HIGH at a time, and produces an N-bit binary output code identifying which input is active.
| Output bit | Boolean Expression | HIGH when input is… |
|---|---|---|
| X₀ (LSB) | D₁ + D₃ + D₅ + D₇ | D₁, D₃, D₅, or D₇ |
| X₁ | D₂ + D₃ + D₆ + D₇ | D₂, D₃, D₆, or D₇ |
| X₂ (MSB) | D₄ + D₅ + D₆ + D₇ | D₄, D₅, D₆, or D₇ |
| Output | Expression |
|---|---|
| X₀ | D₁ + D₃ + D₅ + D₇ + D₉ |
| X₁ | D₂ + D₃ + D₆ + D₇ |
| X₂ | D₄ + D₅ + D₆ + D₇ |
| X₃ | D₈ + D₉ |
A priority encoder handles simultaneous inputs by always outputting the code for the highest-numbered active input. If D₄ and D₈ are both HIGH, the output is BCD for 8 (D₈ has higher priority).
| Output | Priority expression (highest input wins) |
|---|---|
| X₀ | D₁·D̄₂·D̄₄·D̄₆·D̄₈ + D₃·D̄₄·D̄₆·D̄₈ + D₅·D̄₆·D̄₈ + D₇·D̄₈ + D₉ |
| X₁ | D₂·D̄₄·D̄₅·D̄₈·D̄₉ + D₃·D̄₄·D̄₅·D̄₈·D̄₉ + D₆·D̄₈·D̄₉ + D₇·D̄₈·D̄₉ |
| X₂ | D₄·D̄₈·D̄₉ + D₅·D̄₈·D̄₉ + D₆·D̄₈·D̄₉ + D₇·D̄₈·D̄₉ |
| X₃ | D₈ + D₉ |
Key ICs: 74147 Decimal-to-BCD priority encoder (active-low I/O) 74148 Octal-to-binary priority encoder (active-low I/O, enable input, cascade outputs for hex expansion)
Compares two binary numbers P and Q and asserts one of three outputs: P>Q, P=Q, or P<Q. The XNOR gate is the 1-bit equality detector — it outputs 1 when both bits are identical.
| Condition | Boolean Expression |
|---|---|
| Pₛ = Qₛ | (P₃⊙Q₃)·(P₂⊙Q₂)·(P₁⊙Q₁)·(P₀⊙Q₀) — AND of all XNOR bit equalities |
| Pₛ > Qₛ | P₃·Q̄₃ + (P₃⊙Q₃)·P₂·Q̄₂ + (P₃⊙Q₃)·(P₂⊙Q₂)·P₁·Q̄₁ + … ·P₀·Q̄₀ |
| Pₛ < Qₛ | P̄₃·Q₃ + (P₃⊙Q₃)·P̄₂·Q₂ + (P₃⊙Q₃)·(P₂⊙Q₂)·P̄₁·Q₁ + … ·P̄₀·Q₀ |
Adds or verifies a parity bit to detect single-bit transmission errors. Built from a tree of XOR gates — XOR naturally counts odd numbers of 1s.
PLDs are MSI/LSI chips containing arrays of AND and OR gates with fusible (programmable) interconnections. A designer programs the device by selectively blowing fuses to implement any desired SOP Boolean function, replacing many discrete ICs with a single chip.
| Device | Function | Select/Control Lines | Key ICs |
|---|---|---|---|
| MUX N:1 | Routes one of N inputs to 1 output | log₂(N) select + enable | 74151A (8:1), 74150 (16:1) |
| DEMUX 1:N | Routes 1 input to one of N outputs | log₂(N) select + enable | 74138 (1:8), 74154 (1:16) |
| Decoder N-to-2ᴺ | Activates one of 2ᴺ outputs | N inputs + enable | 74138 (3-to-8), 74LS42 (BCD-to-10) |
| Encoder 2ᴺ-to-N | Converts one active input to N-bit code | 2ᴺ inputs | 74147 (priority, active-low) |
| Priority encoder | Encodes highest-active input | 2ᴺ inputs + enable | 74147 (decimal), 74148 (octal) |
| Comparator | P>Q, P=Q, P<Q outputs | Two N-bit inputs + cascade | 7485 (4-bit, cascadable) |
| Parity Gen/Chk | Generate or verify parity bit (XOR tree) | N data inputs + parity in | 74180 (8-bit) |
| BCD→7-seg | Drives 7-segment LED display | 4-bit BCD input | 7447 (15V), 7446 (30V) |
| FPLA | Programmable AND + programmable OR | User-programmed fuses | 840: 14in, 32 AND, 6 OR |
| PAL | Programmable AND + fixed OR | User-programmed AND fuses | Standard PAL families |
| PROM | Fixed AND (all minterms) + programmable OR | Address = input; data = output | 16×4, 256×8 etc. |
| MUX boolean function rule | Data input Xᵢ |
|---|---|
| Output = 0 for both A=0 and A=1 | 0 |
| Output = 1 for both A=0 and A=1 | 1 |
| Output = A (0 when A=0, 1 when A=1) | A |
| Output = Ā (1 when A=0, 0 when A=1) | Ā |