SystemVerilog Series — Complete Index — VLSI Trainers

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VLSI Trainers · SystemVerilog Series

Complete SystemVerilog Series Index

Every post in the series, in order. Click any card to go directly to that article.

42Total Posts

4Phases

27Core SV Topics

0Prerequisites Beyond Basics

Welcome to the SystemVerilog Series 👋

What this series is, who it’s for, what you’ll learn, and how we approach every post — read this first.

Phase 1 Language Foundation

What SV adds over Verilog-2001 and the design philosophy behind it

Integer, real, string, time literals; X, Z, and based number notation

bit, logic, byte, int, real, shortreal, string, chandle, void — and when to use each

Packed & Unpacked Arrays

Dimensions, slices, memory layout differences, and multi-dimensional indexing

new(), delete(), runtime sizing, and common dynamic array patterns

Associative Arrays, Queues & Array Methods

Key-value maps, FIFO queues, sort, find, unique, and all built-in array manipulation methods

Data Declarations & Constants

parameter, localparam, const, typedef, enum, struct, union declarations

Variables, Scope, Nets & Type Compatibility

Lifetime, visibility, net types, implicit conversions, and type-checking rules

The (* *) syntax and how tools use attributes for synthesis and lint hints

Operators & Expressions

Arithmetic, logical, bitwise, relational, shift, conditional, and reduction operators

Real Operators, Size, Sign, Precedence & Built-in Methods

Expression sizing rules, signed/unsigned, operator precedence, and string/integer methods

Concatenation, Array, Struct & Tagged Union Expressions

Static prefixes, replication, aggregate expressions, and tagged union access

Aggregate Expressions, Operator Overloading, Streaming & inside

Streaming operators {<<}, {>>}, the inside operator, and overloaded operators in classes

Phase 2 Hardware Modelling

Procedural Statements & Control Flow

if-else, unique if, priority if, case, unique case, casex, casez

Loops, Jump Statements, Final Blocks & Labels

for, while, do-while, foreach, repeat, break, continue, return, final blocks

Disable, Event Control, Level-Sensitive Sequences & Procedural Assign

disable, @, wait, wait fork, and the deprecated procedural assign/deassign

Processes — always_comb, always_ff, always_latch & Continuous Assignments

When to use which always variant, implicit sensitivity lists, and assign statements

fork…join, Process Threads & Fine-Grain Process Control

join, join_any, join_none, disable fork, wait fork, and process handles

Tasks, Functions & Argument Passing

Automatic vs static, input/output/inout/ref directions, default values, prototype declarations

Scheduling Semantics

The stratified event scheduler — eleven time-slot regions, the iterative loop, and PLI callbacks

Phase 3 Verification

Classes, Objects & Methods

Full OOP model — inheritance, virtual, polymorphism, casting, handles, constructors

Random Constraints

rand, randc, constraint blocks, solve-before, dist, inside, weighted randomisation

Interprocess Synchronization

Semaphores, mailboxes, typed mailboxes, events, wait_order, event merging and null

Clocking Blocks

Input/output skew, #1step, ## cycle delay, default clocking, synchronous drives

Reactive region scheduling, race elimination, $exit, blocking tasks from programs

Assertions — Immediate & Concurrent Overview

Immediate assertions, severity levels, sampled values, the triggered property, boolean expressions

## concatenation, [*] [->] [=] repetition, throughout, within, binsof, local variables, subroutines on match

Properties, Multi-Clock, Concurrent Assertions & Binding

|-> and |=>, disable iff, recursive properties, multi-clock, assert/assume/cover, bind

Coverage — covergroup, Points & Classes

Covergroup as a type, coverage points, cross, clocking events, formal arguments, embedded in classes

Coverage Points, Cross, Options & Methods

Bins, transitions, wildcard, ignore/illegal bins, binsof, instance/type options, coverage methods

Phase 4 Integration & The Language Ecosystem

Hierarchy — Packages, $unit, $root & Modules

Packages, import/::, compilation-unit scope, nested modules, extern modules, timeunit/timeprecision

Ports, Module Instances, Port Rules & Name Spaces

.name, .* connections, port direction inheritance, variable port rules, eight name spaces

Modports, clocking blocks, tasks/functions, export/import, extern forkjoin, virtual interfaces

Typed value parameters, type parameters, $isunbounded, $ token, parameterised checkers

Configuration Libraries

Libraries, cells, config declarations, and the one SV extension to the cell set

System Tasks & System Functions

$typeof, $bits, array query functions, assertion control tasks, $readmem/$writemem, multi-dim arrays

How SV types map into standard VCD waveform dumps — packed arrays, structs, enums

Compiler Directives

`define enhancements — `” `\`” “ tokens, macro-based `include, angle-bracket `include form

Deprecated Features

Why defparam and procedural assign/deassign are deprecated — the problems and the alternatives

Direct Programming Interface (DPI)

import/export, pure/context qualifiers, open arrays, WYSIWYG principle, disable protocol

Series Complete

You Made It — A Look Back at Everything 🎉

A casual recap of every major skill and concept you picked up across all 27 SV posts.

Test Your Knowledge

SystemVerilog Test-Series 1 📝

Practice questions covering every phase of the series — from data types and operators to assertions, coverage, and DPI.

Test Your Knowledge

SystemVerilog Test-Series 2 📝

Practice questions covering every phase of the series — from data types and operators to assertions, coverage, and DPI.