CPOL, CPHA, and the four SPI timing modes — how clock polarity and phase interact to define exactly when data is driven and sampled. All four modes with waveforms and worked examples.
When two chips communicate over SPI, they must agree not just on what data to exchange, but on when the data must be stable and when it is sampled. Different SPI peripheral manufacturers made different choices here, leading to four valid timing configurations. Neither master nor slave can change this after fabrication — it is fixed in the hardware design of each peripheral.
If the master and slave are configured for different timing modes, bits will be sampled at the wrong clock edges, and every byte received will be corrupted silently — SPI has no built-in error detection. This makes understanding timing modes one of the most practically important aspects of working with SPI in real designs.
Clock Polarity (CPOL) defines what level SCLK holds when the channel is idle — that is, when no exchange is in progress (SS is HIGH).
CPOL determines the idle level of SCLK and therefore which edge is the “first” edge after SS asserts LOW.
Clock Phase (CPHA) determines the relationship between when data is driven onto the bus and when it is sampled. It answers the question: on which edge does the receiver latch each bit?
CPHA=0 (top): data is set up before the first clock edge; sampled on each first (rising) edge. CPHA=1 (bottom): data is driven on each first edge; sampled on each second (falling) edge — giving a full half-period of setup time.
CPOL and CPHA each have two possible values, giving exactly four combinations. These are commonly numbered Mode 0 through Mode 3:
| Mode | CPOL | CPHA | Clock idle level | Data sampled on | Used by |
|---|---|---|---|---|---|
| Mode 0 | 0 | 0 | LOW | Rising (1st) edge | Most common — Arduino default, many ADCs |
| Mode 1 | 0 | 1 | LOW | Falling (2nd) edge | Some SD cards, CAN controllers |
| Mode 2 | 1 | 0 | HIGH | Falling (1st) edge | Some ADCs, certain sensors |
| Mode 3 | 1 | 1 | HIGH | Rising (2nd) edge | ST7735 display, MAX31865 |
The most widely used mode. SCLK idles LOW. Data (MOSI and MISO) is set up half a clock period before the first rising edge, then sampled on each rising edge and changed on each falling edge.
Mode 0 (CPOL=0, CPHA=0, MSB first). MOSI transmits 0xA5; MISO returns 0x3C. Both lines are sampled simultaneously on every rising clock edge.
SCLK still idles LOW (CPOL=0), but now data is driven on the rising edge and sampled on the falling edge. This gives a full half-period of setup time before each sample.
Mode 1 (CPOL=0, CPHA=1). Data is driven on each rising edge and sampled on the following falling edge. The don’t-care region at the start is longer than in Mode 0 — no data is ready until SS goes low AND the first rising edge occurs.
SCLK idles HIGH (CPOL=1). The first clock edge is therefore a falling edge. With CPHA=0, data is set up before this first falling edge and sampled on it. Data then changes on the rising edges between bits.
Mode 2 (CPOL=1, CPHA=0, LSB first). Clock idles HIGH. Sampled on falling edges. Notice how the clock waveform is the inversion of Mode 0.
SCLK idles HIGH (CPOL=1). Data is driven on the first (falling) edge and sampled on the second (rising) edge. This is the mirror of Mode 1, and like Mode 0 and Mode 3 share the same sample edge polarity (rising).
Mode 3 (CPOL=1, CPHA=1, LSB first). Clock idles HIGH. Data driven on falling edges, sampled on rising edges — same sample polarity as Mode 0, but inverted idle state.
The SPI protocol does not specify which end of a byte is transmitted first. Both master and slave must use the same bit ordering or every received byte will be bit-reversed.
Byte to transmit: 0xA5 = 1010 0101₂
MSB first (bit 7 → bit 0): 1 0 1 0 0 1 0 1
First bit on wire = bit 7 = 1. Last bit = bit 0 = 1.
LSB first (bit 0 → bit 7): 1 0 1 0 0 1 0 1
First bit on wire = bit 0 = 1. Last bit = bit 7 = 1.
In this example both orderings happen to produce the same sequence because 0xA5 is palindromic. Try with 0xB5 = 1011 0101:
MSB first: 1 0 1 1 0 1 0 1 → receiver sees 0xB5
LSB first: 1 0 1 0 1 1 0 1 → receiver reassembles as 0xAD if it reads MSB-first
Rule: Always check whether the peripheral datasheet specifies MSB or LSB first. Most modern SPI peripherals use MSB-first. The UART and I²C protocols, by contrast, always use LSB-first.
When implementing an SPI master in SystemVerilog, CPOL determines the reset value of your SCLK output register (sclk_r <= CPOL), and CPHA determines whether you drive MOSI on the first or second clock edge of each bit period. A parameterised SPI master module will have CPOL and CPHA as parameters so the same RTL can target any timing mode. RTL interview questions frequently ask you to implement SPI — the first thing you say should be: "What are the CPOL and CPHA requirements?"
The aperture time concept from SPI-01 maps directly to STA (Static Timing Analysis) in VLSI. CPHA=1 gives one full half-period (t_period/2) of setup time before the sample edge — this is exactly the concept of setup time margin in STA. The falling edge of SCLK (the "drive" edge in Mode 1) corresponds to the launch edge in STA, and the rising edge (the "sample" edge) corresponds to the capture edge. SCLK frequency must be low enough that propagation delay through the slave's combinational logic fits within the half-period.
When debugging an SPI bus on a PCB with a logic analyser (e.g. Saleae, Rigol), the first configuration step is always selecting CPOL and CPHA. An incorrectly configured decoder will silently produce wrong decoded values — the most common error is leaving CPOL=0 CPHA=0 when the actual device uses Mode 3. The waveform shapes in this article give you the visual intuition to identify the mode from the oscilloscope trace before you even open a datasheet: if SCLK is HIGH between transactions → CPOL=1. If data is stable for one full half-period before and after sample edge → CPHA=0.