Communication channels, synchronous vs asynchronous protocols, and a complete introduction to Serial Peripheral Interface — the four wires, master-slave architecture, and why SPI is everywhere.
A communication channel is a physical set of wires that conveys data between two or more entities. The entities could be modules on the same semiconductor chip, separate chips on a PCB, chips connected by cables, or nodes on a network.
A communication protocol is the set of rules governing how that channel operates — who can send data and when, how data is clocked in and out, and whether acknowledgements or error detection are included.
Protocols are designed around specific constraints. The most important two are distance and performance vs cost:
| Scope | Distance | Example Protocols |
|---|---|---|
| On-chip | < 10 mm | AXI, Avalon |
| Chip-to-chip | < 1 m | PCIe, QPI, RapidIO, SPI |
| Local area network | < 100 m | Ethernet, InfiniBand |
| Protocol | Bandwidth per channel | Key cost factor |
|---|---|---|
| PCIe Gen4 | ~4 GB/s | Precise impedance matching required |
| USB 3.1 | ~10 Gb/s | Differential signalling circuitry |
| SPI | ~100 MB/s | No impedance matching required |
A fundamental challenge in any communication channel is making sure the receiver samples each bit at exactly the right moment — not too early, not too late. This leads to two broad protocol families:
The clock is not embedded in the channel. Both transmitter and receiver must agree in advance on the clock frequency, or the receiver must extract the clock from the data stream itself.
The transmitter clock is embedded in the channel as a dedicated wire. Transmitter and receiver share the same clock — no clock recovery needed. SPI, I²C, and on-chip protocols like AXI all use a shared clock.
SCLK wire carries the clock, which the master always drives. This is what makes SPI reliable and simple to implement — there is no ambiguity about when to sample each bit.
Even with a shared clock, there is still a constraint: the transmitter must not change a bit value at the same moment the receiver is sampling it. The window around the sampling edge where data must remain stable is called the aperture time.
Receiver samples on each rising edge of its clock. The red shaded zones (aperture times) show when data must not change. Bit transitions (purple) occur between clock edges — safely outside the aperture. If a transition fell inside the aperture, metastability could occur.
If a bit transition happens inside the aperture time, the receiver’s flip-flop may capture an indeterminate value — neither a valid 0 nor 1. This is metastability. In synchronous designs, careful timing analysis ensures transitions always land safely between sample edges. SPI addresses this through CPOL and CPHA settings (covered in SPI-02).
Serial Peripheral Interface (SPI) is precisely characterised by five properties. Understanding each word in the description is the foundation for understanding the protocol:
| Property | Meaning |
|---|---|
| Bidirectional | Data flows simultaneously in both directions — master→slave and slave→master at the same time |
| Single-ended | One wire per signal (vs differential signalling like LVDS where each signal uses two wires) |
| Master-slave | One entity (master) initiates all communication; slaves only respond |
| Synchronous | A clock signal is embedded in the channel — data is sampled on clock edges |
| Serial | Bits are transmitted one at a time, not in parallel |
SS=1 means the channel is idle; SS=0 means the master is addressing this slave and an exchange is in progress.The four SPI wires. Three are driven by the master (SCLK, SS, MOSI); one is driven by the slave (MISO). MOSI and MISO carry data simultaneously during an exchange.
SPI is a single-master bus. There is exactly one entity that can initiate communication at any time — the master. Slaves can only respond to requests; they cannot spontaneously send data to the master.
This simplifies the protocol enormously — there is no arbitration, no collision detection, no address negotiation. The master is always in control. The trade-off is that slaves cannot interrupt the master to signal that data is ready (unlike I²C which allows a limited form of this).
When no exchange is happening:
SS = 1 (high) — channel is idle, no slave is being addressedSCLK holds the idle value defined by CPOL (0 by default)MOSI and MISO values are don’t-caresSPI idle state with CPOL=0. SS is high (channel idle), SCLK holds 0 (CPOL=0 idle level), MOSI and MISO are don’t-cares (hatched regions).
The fundamental unit of SPI communication is the exchange. One exchange transfers exactly 8 bits simultaneously in both directions — 8 bits from master to slave (on MOSI) and 8 bits from slave to master (on MISO).
During an exchange:
SS → LOW to beginSS → HIGH to endCPOL=0, CPHA=0, MSB-first SPI exchange. MOSI transmits 0xA5 from master to slave; MISO simultaneously transmits 0x3C from slave to master. Data is sampled on each of the 8 rising clock edges (purple dashed lines). Don’t-care regions shown as hatched.
Given: CPOL=1, CPHA=1, MSB-first. The MISO signal shows (left to right, between SCLK edges): 1, 0, 1, 1, 0, 1, 0, 1
Step 1 — Identify the sample edge. CPOL=1 → clock idles HIGH → first edge is FALLING. CPHA=1 → data sampled on the SECOND edge = RISING edge.
Step 2 — Read bits. MSB-first → read left to right: 1, 0, 1, 1, 0, 1, 0, 1
Step 3 — Assemble the byte. 10110101₂ = 0xB5
This is the exact exercise from the textbook on page 7 — the MISO value sent from slave to master is 0xB5.
Shift registers: The SPI exchange is physically implemented using SIPO and PISO shift registers (from DE-09). The master’s MOSI output feeds the slave’s SIPO shift register; the slave’s PISO shift register drives MISO. Both shift registers clock on the same SCLK — the “handshake” is automatic.
Scan chains used in Design for Testability (DFT) are structurally identical to SPI. The scan-in (SI) wire is MOSI, scan-out (SO) is MISO, scan enable (SE) is equivalent to SS, and the test clock (TCK) is SCLK. Both capture and shift-out test patterns using exactly the same shift-register mechanism. Understanding SPI thoroughly means you already understand how scan chains load and unload test data.
SPI peripherals appear in virtually every SoC: boot-ROM configuration, ADC/DAC interfaces, EEPROM programming, FPGA configuration, display driver ICs (MAX7219, ST7735), and power management ICs. Writing a SystemVerilog SPI master is one of the most common RTL interview exercises — it directly tests your understanding of CPOL/CPHA, shift register design, and state machine coding.