SPI-03: The SPI Exchange — Timing Diagrams & Worked Examples — VLSI Trainers
SPI Series · Article 3 of 6
SPI-03: The SPI Exchange
How to read and draw SPI timing diagrams. All four exchange examples from the protocol specification — Mode 0 through Mode 3 — with annotated waveforms and three fully worked decoding exercises.
📊What Is a Timing Diagram?
A timing diagram is the primary tool for describing and debugging digital protocols. Understanding how to read one is a foundational skill for every VLSI and embedded systems engineer.
Figure 1 — Anatomy of a timing diagram
Key elements of a timing diagram: signal rows (each one wire), horizontal axis = time, HIGH/LOW levels for single-bit signals, angled transition lines showing bus changes, hatched regions for don’t-care values, and the exchange window defined by SS being LOW.
Reading rules
Each row is one physical wire. The vertical space shows HIGH (top) and LOW (bottom).
Steep angled lines = transitions. A steep rise is a rising edge; a steep fall is a falling edge. The horizontal position of the edge matters — that is when it occurs relative to other signals.
Hatched / shaded regions = don’t-care. The value during this period is undefined or irrelevant to the protocol.
Angled crossing lines on data buses = bus transitions. When two diagonal lines cross, the data value is changing at that instant. Values are stable and valid in the flat regions between transitions.
Dashed vertical lines = reference markers. These often show sample points or event boundaries.
📐Anatomy of an SPI Exchange
Every SPI exchange, regardless of mode, follows the same four-phase structure:
Phase
What happens
Who acts
1. Assert SS
SS transitions HIGH → LOW. Signals the selected slave that an exchange is starting. SCLK has not started pulsing yet.
Master
2. Data setup
MOSI and MISO are driven to the first bit value. Timing of this relative to the first clock edge depends on CPHA.
Master (MOSI) & Slave (MISO)
3. 8 clock cycles
SCLK pulses 8 times. On each sample edge: master latches MISO bit, slave latches MOSI bit. On each drive edge: next bit placed on MOSI/MISO.
Master (SCLK, MOSI) & Slave (MISO)
4. Deassert SS
SS transitions LOW → HIGH. Exchange is complete. Both sides now have a complete 8-bit byte.
Master
Critical constraint: SS must stay LOW for exactly 8 complete clock cycles (one exchange). Deasserting SS early aborts the exchange. For multi-exchange transactions, SS stays LOW across multiple 8-cycle groups — covered in SPI-04.
🗺️How to Read Any SPI Waveform in 5 Steps
A systematic approach works for any CPOL/CPHA combination. Apply these steps in order:
1
Find the exchange boundaries. Locate where SS goes LOW (exchange start) and HIGH (exchange end). Everything outside these boundaries is idle — ignore it.
2
Identify CPOL from the idle SCLK level. SCLK HIGH between exchanges → CPOL=1. SCLK LOW → CPOL=0. This tells you which edge is “first”.
3
Identify CPHA from when data first appears. If MOSI/MISO data is set up before the first clock edge (half-cycle early) → CPHA=0. If data first changes on the first clock edge → CPHA=1.
4
Find the sample edges. CPHA=0 → sample on 1st edge of each bit period. CPHA=1 → sample on 2nd edge. Read the MOSI/MISO value at each sample edge — that is the bit captured by the receiver.
5
Assemble the byte. Check bit order (MSB-first or LSB-first — from the datasheet or specified in the problem). MSB-first → first captured bit = bit 7. LSB-first → first captured bit = bit 0. Convert the 8-bit sequence to hex.
Pro tip for stable regions: In CPHA=1, the data value is most clearly readable in the middle of each bit period — between the drive edge and the sample edge. Look for the flat plateau on the MOSI/MISO line within each half-cycle pair.
①Exchange 1 — CPOL=0, CPHA=0, MSB First
The most common SPI configuration (Mode 0). SCLK idles LOW. Data is set up half a cycle before the first rising edge. Bits are sampled on each rising edge. Data changes on each falling edge.
Exchange 1 (CPOL=0, CPHA=0, MSB first). Master sends 0xD3 on MOSI; slave responds with 0x5A on MISO. Bits sampled on each of the 8 rising edges (purple dashed). Data set up before first edge and changes on falling edges.
②Exchange 2 — CPOL=0, CPHA=1, MSB First
SCLK still idles LOW but now data is first driven on the rising edge (not before it). Bits are sampled on each falling edge — the second edge of each bit period. This means the 8 bits are sampled on the 2nd through 9th clock edges overall.
Exchange 2 (CPOL=0, CPHA=1, MSB first). Same bytes as Exchange 1 but sampled on falling edges. The don’t-care region is longer at the start — data is not valid until the first rising clock edge occurs.
Comparing Exchange 1 and 2: The decoded values are identical (MOSI=0xD3, MISO=0x5A) because the data content is the same — only the timing relationship between data and clock edges changed. In practice you must not mix modes: if the master is Mode 0 and the slave is Mode 1, the receiver latches a bit one clock cycle too late and gets completely wrong data.
③Exchange 3 — CPOL=1, CPHA=0, LSB First
SCLK idles HIGH (CPOL=1). The first clock edge is therefore a falling edge. With CPHA=0, data is set up before this first falling edge and sampled on it. Note this exchange uses LSB first — the first bit on the wire is bit 0 of each byte.
Exchange 3 (CPOL=1, CPHA=0, LSB first). SCLK idles HIGH — the first clock edge is falling. Bits sampled on falling edges. Because this is LSB-first, the received bit sequence must be reversed before assembling the byte.
④Exchange 4 — CPOL=1, CPHA=1, MSB First
SCLK idles HIGH and data is driven on the first (falling) edge. Bits are sampled on the rising edge — the second edge of each bit period. Like Mode 0, this samples on rising edges, but the idle state is inverted. This is the exchange used in the textbook’s decode exercise.
Figure 5 — Exchange 4: CPOL=1, CPHA=1, MSB first — the textbook exercise
Exchange 4 (CPOL=1, CPHA=1, MSB first). This is the exact waveform from the textbook exercise on page 7. The MISO line carries 0xB5 — read at each rising edge after the corresponding data is driven on the falling edge before it.
✏️Worked Decode Exercises
🔍 Exercise 1 (Textbook) — Decode MISO from Exchange 4
Given: CPOL=1, CPHA=1, MSB first. Refer to Figure 5 above. What byte did the slave send to the master on MISO?
1
Exchange boundaries: SS goes LOW at the start, HIGH at the end. 8 clock cycles occur.
2
CPOL: SCLK is HIGH before SS asserts → CPOL=1. First clock edge is falling.
3
CPHA: MISO data doesn’t change until the first falling edge → CPHA=1. Sample on rising edges (2nd, 4th, 6th, 8th … edge overall).
4
Read MISO at each rising edge (left to right):1, 0, 1, 1, 0, 1, 0, 1
5
MSB first → bit 7 first: 1011 0101₂ = 0xB5
✓ MISO = 0xB5
🔍 Exercise 2 — Decode MOSI from Exchange 1
Given: CPOL=0, CPHA=0, MSB first. From Figure 2, the MOSI line shows (reading the stable values at each rising edge, left to right): 1, 1, 0, 1, 0, 0, 1, 1. What byte did the master send?
1
Sample edge: CPOL=0 → first edge rising. CPHA=0 → sample on 1st (rising) edge. Rising edges are the sample points.
2
Bits read at rising edges:1, 1, 0, 1, 0, 0, 1, 1
3
MSB first → bit 7 = 1: 1101 0011₂ = 0xD3
✓ MOSI = 0xD3
🔍 Exercise 3 — Identify Mode from a Waveform
Given: You probe an SPI bus. You observe:
SCLK is HIGH when SS is deasserted (between transactions)
When SS goes LOW, MOSI changes value immediately on the first clock edge (you see data being driven on the first edge after SS asserts)
The datasheet says bits are sampled on rising edges
1
CPOL: SCLK is HIGH between transactions → CPOL=1. First clock edge is falling.
2
CPHA: Data changes on the first (falling) clock edge, not before it → CPHA=1. Sampled on second (rising) edge — matches the datasheet.
3
Mode = CPOL=1, CPHA=1 → Mode 3. This is Exchange 4 (Figure 5).
✓ Mode 3 (CPOL=1, CPHA=1)
🔬VLSI Connections
🔬 Reading datasheets — the timing diagram is the spec
When you integrate an SPI peripheral IC into an SoC, the peripheral’s timing diagram in its datasheet is the authoritative specification. Every timing parameter — setup time, hold time, SCLK frequency limit, SS assertion time — is read directly from diagrams exactly like the ones in this article. RTL engineers write timing assertions in SystemVerilog (using $rose(sclk), $fell(ss)) that formally verify the RTL matches the timing diagram. A mistake in reading the diagram propagates all the way to tapeout bugs.
🔬 Shift register hardware behind the waveform
Each SPI exchange is physically implemented by two 8-bit shift registers — one in the master, one in the slave — clocked by SCLK. On each clock edge: the MSB (or LSB) of the master’s shift register shifts out onto MOSI while a new bit shifts in from MISO at the LSB. The slave simultaneously does the same in reverse. After 8 edges, the two shift registers have exchanged their full contents. This is why understanding DE-09 (shift registers) is a prerequisite for SPI — the waveform is the shift register operation.
🔬 Protocol-aware testbenches in SystemVerilog
SV verification of an SPI slave begins with a BFM (Bus Functional Model) that drives the four SPI signals correctly. The BFM must implement the CPOL/CPHA parameters, generate SCLK, drive MOSI bit by bit on the correct edges, and sample MISO on the correct edges. Clocking block inputs in SVA use #1step skew to sample signals just before the clock edge — exactly the concept you just learned as “sample before the aperture time”. Writing an SPI BFM from scratch is a standard RTL/verification interview exercise at Qualcomm, ARM, and similar companies.
Summary — SPI-03 key points: A timing diagram shows signal states over time — high/low levels, transitions (edges), and don’t-care regions. Every SPI exchange: SS asserts, 8 clock cycles, data sampled on the correct edge, SS deasserts. Use the 5-step decode method: find SS boundaries → read CPOL → read CPHA → locate sample edges → assemble byte with correct bit order. CPHA=1 produces stable readable data plateaus between drive-edge and sample-edge — easier to decode visually than CPHA=0.