DE-08: Flip-Flops β€” VLSI Trainers
Digital Electronics Series · DE-08

Flip-Flops

RS latch with NOR and NAND gates β€” race analysis β€” clocked RS β€” D flip-flop β€” JK flip-flop and race-around β€” Master-Slave JK β€” edge-triggered T flip-flop β€” asynchronous PRESET/CLEAR β€” excitation tables β€” flip-flop conversion with worked examples.

πŸ” Sequential Circuits & Memory

In combinational circuits (DE-05, DE-06), outputs depend only on current inputs. Sequential circuits add memory β€” the output depends on both current inputs and past history. The basic memory element storing one bit is the flip-flop.

RS Flip-Flop
Set-Reset latch. Simplest FF. Forbidden state when both inputs HIGH. Built from NOR or NAND gates.
Clocked RS
RS with clock enable. Synchronous β€” output changes only on active clock edge. Still has forbidden state.
D Flip-Flop
Data/Delay FF. One input β€” eliminates forbidden state. Q follows D on clock edge. Used in registers.
JK Flip-Flop
Universal FF. J=K=1 causes toggle β€” no forbidden state. Most versatile. Race-around solved by edge-trigger or Master-Slave.
T Flip-Flop
Toggle FF. T=0: hold. T=1: complement output on each clock. Built from JK with J=K=T. Used in counters.
Master-Slave
Two FFs in series. Master active on clock HIGH, Slave on clock LOW. Eliminates race-around. Pulse-triggered.

πŸ”’ RS Latch with NOR Gates

The RS latch is the simplest memory element β€” two cross-coupled NOR gates where each gate’s output feeds back to the other’s input. S = Set (forces Q=1), R = Reset (forces Q=0). The outputs Q and QΜ„ are always complements β€” except in the forbidden state.

RS Latch β€” Cross-Coupled NOR Gates S Q R QΜ„ RS NOR Latch Characteristic Table S R Q(n+1) QΜ„(n+1) Mode 0 0 Q(n) QΜ„(n) HOLD (no change) 0 1 0 1 RESET (Q=0) 1 0 1 0 SET (Q=1) 1 1 0 0 FORBIDDEN (Q=QΜ„!) Avoid: Q and QΜ„ both 0
Figure 1 β€” RS NOR latch. Dashed lines show cross-coupling feedback. S=1 forces Q=1; R=1 forces Q=0; S=R=0 holds previous state. The forbidden condition S=R=1 makes both outputs 0 β€” they are no longer complements, and when inputs return to 00, the outcome is unpredictable (critical race).

🏁 Race Conditions

When the RS latch transitions between states, both gates must change simultaneously β€” but propagation delays differ. This causes a race between the two flip-flop transitions.

Race typeCauseOutcomeAcceptable?
Valid (non-critical) raceRS changes from 10 or 01 to 00 β€” both gates race, but both paths lead to the same stable statePredictable β€” same stable state regardless of which gate winsYes βœ“
Critical raceRS changes from 11 to 00 β€” one path reaches stable A (Q=0,QΜ„=1) and another reaches stable B (Q=1,QΜ„=0)Unpredictable β€” outcome depends on inherent gate delays, which the designer cannot controlNo βœ—
The rule: Never allow RS = 11 in an NOR RS latch. If the inputs transition from 11 β†’ 00, the critical race makes the final state completely unpredictable. In NAND latch the equivalent forbidden state is RS = 00.

πŸ”’ RS Latch with NAND Gates (Active-HIGH RS)

Applying De Morgan’s theorem to the NOR latch gives an equivalent NAND latch. Two cross-coupled NAND gates with NOT gates on the inputs produce an active-HIGH RS latch β€” identical characteristic table to the NOR version, forbidden state still S=R=1.

Key equivalence: NOR latch (with active-HIGH S,R inputs) and NAND latch (with inverters on inputs) are logically identical. The De Morgan transformation converts one to the other: NAND(Δ€,BΜ„) = NOR(A,B).

πŸ”’ Active-Low NAND RS Latch

Without the input inverters, the NAND latch has active-LOW SΜ„ and RΜ„ inputs. The characteristic table is inverted: SΜ„=RΜ„=1 is the HOLD state; SΜ„=0,RΜ„=1 SETs; SΜ„=1,RΜ„=0 RESETs; SΜ„=RΜ„=0 is the forbidden state.

SΜ„RΜ„Q(n+1)Mode
11Q(n)HOLD
011SET (Q=1)
100RESET (Q=0)
00FORBIDDEN β€” both outputs go HIGH

This active-low NAND latch is the core of all TTL flip-flop ICs β€” the PRESET and CLEAR asynchronous inputs are active-low precisely because of this latch topology.

⏱️ Clocked RS Flip-Flop

Adding two AND gates (or NAND gates) in front of the latch creates a synchronous flip-flop β€” the latch only responds to inputs when the clock (CLK) is HIGH. When CLK=0 the AND gates block R and S, holding the latch in HOLD mode regardless of input changes.

Clocked RS Flip-Flop — AND Gates Gate the Clock S CLK AND R AND NOR Latch Q Q̄ Clocked RS Operation CLK=0: AND gates block → HOLD regardless of S,R CLK=1, S=0, R=0: HOLD (retain previous state) CLK=1, S=1, R=0: SET (Q→1) CLK=1, S=0, R=1: RESET (Q→0); S=R=1: FORBIDDEN
Figure 2 β€” Clocked RS flip-flop. The AND gates are “loading gates” β€” they pass S and R to the latch only during CLK=1. Q(n+1) = SΒ·CLK + Q(n)Β·RΜ„Β·CLK. Changes propagate on the leading edge of the clock pulse (level-triggered).

πŸ“Ά Level Triggering vs Edge Triggering

Two different ways to determine when a flip-flop samples its inputs:

TypeWhen FF respondsSymbol on CLK pinProblem
Level-triggeredOutput can change any time CLK is HIGH (or LOW)No symbolMultiple transitions possible during one clock pulse
Positive edge-triggeredOnly on LOW→HIGH transition (rising edge)Small triangle ▷None — inputs must be stable only around the edge
Negative edge-triggeredOnly on HIGH→LOW transition (falling edge)Triangle with bubble ▷○None

Edge Detector Circuit

A narrow spike at the rising edge is generated by: feed CLK through a NOT gate (propagation delay d), then AND the original CLK with the delayed inverted CLK. The AND output is HIGH only for those few nanoseconds when both CLK=1 and CLKΜ„=1 simultaneously β€” exactly the propagation delay of the inverter, typically 5–10 ns.

πŸ“¦ D Flip-Flop

The D (Data/Delay) flip-flop is a modified clocked RS flip-flop that eliminates the forbidden state by tying S=D and R=DΜ„ β€” the two inputs are always complements. Only one external input D is needed.

D Flip-Flop β€” Symbol, Characteristic Table, and Timing D FF D CLK Q QΜ„ Characteristic Table D    Q(n+1)    Mode 0     0        RESET 1     1        SET Key Properties Q(n+1) = D   β€” output simply follows input No forbidden state β€” S and R are always complements Used in: data registers, pipeline stages, memory cells
Figure 3 β€” D flip-flop symbol and characteristics. The small triangle on the CLK pin indicates positive edge triggering. Q(n+1) = D β€” the output copies the data input on every rising clock edge and holds that value until the next edge.

πŸ”„ JK Flip-Flop & Race-Around Condition

The JK flip-flop is a modified RS flip-flop where J≑S and K≑R, but the outputs are fed back to the AND gates. This means when J=K=1, the latch toggles β€” eliminating the forbidden state entirely.

JKQ(n+1)Mode
00Q(n)HOLD
010RESET
101SET
11QΜ„(n)TOGGLE (complement)

Characteristic equation: Q(n+1) = JΒ·QΜ„(n) + KΜ„Β·Q(n)

Race-Around Condition

When J=K=1 and CLK is HIGH, the output toggles β†’ feedback changes inputs β†’ toggles again β†’ infinite loop during the clock pulse. This is the race-around condition. Two solutions:

  1. Make clock pulse width < propagation delay β€” impractical (delay is unknown)
  2. Use edge-triggered JK flip-flop β€” only responds to the edge, not the level
  3. Use Master-Slave JK flip-flop β€” sections the response into two half-cycles
Race-around is not the same as critical race. Race-around means the flip-flop may toggle multiple times per clock pulse (uncontrolled counting). Critical race means the final stable state is unpredictable. Edge triggering solves race-around; avoiding S=R=11 (or J=K=11 in level-triggered) avoids critical race.

πŸ” Toggle (T) Flip-Flop

The T flip-flop is the simplest sequential element β€” it has a single input T and toggles on every clock edge when T=1. Built by connecting J and K inputs of a JK flip-flop together to form one T input.

TQ(n+1)Mode
0Q(n)HOLD (no change)
1QΜ„(n)TOGGLE (complement)

Key application β€” Frequency Division: If T=1 permanently, the flip-flop toggles on every clock edge. The Q output is exactly half the clock frequency: f_out = f_CLK / 2. Chain n T flip-flops to divide by 2ⁿ β€” the foundation of binary counters (DE-10).

T flip-flop waveform: With T=1 and a 1 MHz clock input, Q alternates every clock cycle β€” giving a 500 kHz square wave at Q. The duty cycle is always exactly 50% regardless of clock duty cycle, because toggle happens on every rising edge.

⚑ Asynchronous PRESET and CLEAR

In practical flip-flops, two additional inputs β€” PREΜ… (Preset) and CLRΜ… (Clear) β€” allow the flip-flop to be set or reset immediately, independent of the clock. They operate asynchronously (no clock needed) and are typically active-LOW.

PREΜ…CLRΜ…QQΜ„Action
11Normal JK operationClock controls output
0110PRESET β€” sets Q=1 immediately
1001CLEAR β€” resets Q=0 immediately
00UndefinedFORBIDDEN β€” both outputs try to be 1
Power-on initialisation. When power is applied to a digital system, all flip-flop states are undefined. PRESET and CLEAR inputs are used in a brief initialisation sequence to set every flip-flop to a known state (usually all 0) before the system clock starts. This is why every real flip-flop IC includes these pins.

πŸ‘₯ Master-Slave JK Flip-Flop

Two JK flip-flops in series with complementary clocking: the Master is enabled when CLK=1; the Slave is enabled when CLK=0 (CLK=1 disables Slave). Because the Slave is disabled while the Master is active, the Master’s output cannot feed back and cause race-around.

Master-Slave JK β€” Two FFs, Complementary Clocking J K MASTER Active when CLK=1 CLKβ†’ inputs directly CLK Qm QΜ„m ! SLAVE Active when CLK=0 Clocked by CLKΜ„ Q QΜ„ Timing CLK rises: Master samples J,K CLK high: Master output changes CLK falls: Slave copies Master Final output changes at ↓CLK
Figure 4 β€” Master-Slave JK. During CLK=1 the Master stores J,K state; during CLK=0 the Slave copies Master output to the final Q. The Slave is disabled while Master is active β€” so the Master’s output cannot feed back and toggle again during the same clock pulse. Pulse-triggered device.

πŸ“‹ Excitation Tables

The characteristic table tells you next state given inputs and current state. The excitation table is the inverse β€” it tells you what inputs are required to achieve a given transition from Q(n) to Q(n+1). Excitation tables are essential for sequential circuit design and flip-flop conversion.

RS Excitation Table
Q(n)Q(n+1)SR
000Ο†
0110
1001
11Ο†0
JK Excitation Table
Q(n)Q(n+1)JK
000Ο†
011Ο†
10Ο†1
11Ο†0
D Excitation Table
Q(n)Q(n+1)D
000
011
100
111
T Excitation Table
Q(n)Q(n+1)T
000
011
101
110
Reading the JK excitation table. Ο† = don’t care. To go 0β†’1: J must be 1 (to set), K is irrelevant. To go 1β†’0: K must be 1 (to reset), J is irrelevant. This is why JK is the most flexible flip-flop β€” it requires fewer constraints on its inputs than RS.

πŸ”§ Flip-Flop Conversion

Any flip-flop type can be converted to any other type by adding a combinational circuit at the input that translates the required flip-flop’s input signals into the given flip-flop’s inputs. The method uses both excitation tables.

Example 8.6 β€” Convert JK flip-flop to RS flip-flop

We have a JK FF and want it to behave as an RS FF. From the RS excitation table, find what J and K must be for each RS transition:

Truth tableCombine RS excitation (S,R inputs) with JK excitation (J,K outputs needed)
0β†’0RS needs S=0,R=Ο†; JK needs J=0,K=Ο† β†’ J=S=0
0β†’1RS needs S=1,R=0; JK needs J=1,K=Ο† β†’ J=S=1
1β†’0RS needs S=0,R=1; JK needs J=Ο†,K=1 β†’ K=R=1
1β†’1RS needs S=Ο†,R=0; JK needs J=Ο†,K=0 β†’ K=R=0
K-mapSimplify: J=S, K=R
Conversion: J = S    K = R    (trivial β€” just rename the inputs)
Example 8.7 β€” Convert D flip-flop to JK flip-flop

We have a D FF and want JK behaviour. For each JK input combination and Q(n), what D input is needed to achieve Q(n+1)?

J=0,K=0Hold: Q(n+1)=Q(n) β†’ D=Q(n)
J=0,K=1Reset: Q(n+1)=0 β†’ D=0
J=1,K=0Set: Q(n+1)=1 β†’ D=1
J=1,K=1Toggle: Q(n+1)=QΜ„(n) β†’ D=QΜ„(n)
K-mapSimplify 4-variable K-map for D(J,K,Q):
D = JΒ·QΜ„ + KΜ„Β·Q

The combinational circuit D = JΒ·QΜ„ + KΜ„Β·Q is added between the JK inputs and the D flip-flop input. This is a 2-gate circuit: one AND-OR network with Q and QΜ„ feedback.

⏱️ Flip-Flop Timing Parameters

ParameterSymbolDefinitionImportance
Propagation delay (clock→Q)t_PLH, t_PHLTime from triggering clock edge to output transition (measured at 50% levels)Limits maximum clock frequency
Set-up timet_sMinimum time data must be stable BEFORE the triggering clock edgeViolated = setup time violation β†’ metastability
Hold timet_hMinimum time data must remain stable AFTER the triggering clock edgeViolated = hold time violation β†’ metastability
Maximum clock frequencyf_maxMaximum clock rate at which FF operates reliablyDetermines system speed limit
Minimum pulse widtht_CH, t_CLMinimum HIGH time and minimum LOW time for the clock pulseSpecified in datasheet β€” must not be violated
Async PRESET/CLEAR delayt_PLH (PRE), t_PHL (CLR)Time from asynchronous input active to output respondingDetermines initialisation speed

πŸ“‹ Quick Reference

FF TypeChar. EquationForbidden / SpecialKey Use
RS (NOR)Q(n+1) = S + RΜ„Β·Q(n)S=R=1 forbidden (both Q=0)Basic latch, input stage
RS (NAND, active-low)Q(n+1) = SΜ„’+ RΜ„’Β·QΜ„(n)SΜ„=RΜ„=0 forbidden (both Q=1)TTL internal latches
DQ(n+1) = DNone β€” no forbidden stateData registers, pipeline
JKQ(n+1) = JΒ·QΜ„ + KΜ„Β·QJ=K=1 β†’ toggle (no forbidden)Universal β€” counters, registers
TQ(n+1) = TβŠ•Q(n)T=1 β†’ toggle; T=0 β†’ holdCounters, frequency dividers
ConversionCombinational logic needed
JK β†’ RSJ = S    K = R
D β†’ JKD = JΒ·QΜ„ + KΜ„Β·Q
JK β†’ DJ = D    K = DΜ„
JK β†’ TJ = T    K = T
Coming next β€” DE-09: Shift Registers β€” SISO, SIPO, PISO, PIPO, Bidirectional, Universal shift registers β€” Ring Counter, Johnson Counter β€” IC details (7491, 74164, 74194, 74195) β€” and applications: Serial Adder, Parity Generator, Time Delay, Data Conversion, Sequence Generator.
← DE-07: Logic Families ↑ All DE Articles DE-09: Shift Registers β†’
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