Digital Electronics Interview Q&A- Post 1 – Your VLSI Journey Starts Here

🔢 Number Systems

Q1 Why do computers use binary (base-2) instead of decimal (base-10)? Easy

“Because a transistor only has two reliable states — on and off. Trying to get it to hold ten different voltage levels reliably at GHz speeds would be a nightmare.”

At the physical level, a transistor is a switch — it is either conducting (logic 1) or not conducting (logic 0). Representing decimal would require ten distinguishable voltage levels from a device that naturally wants to snap between two states. Noise, temperature variation, and process variation would make those intermediate levels ambiguous and unreliable. Binary maps perfectly onto transistor physics: high voltage = 1, low voltage = 0, with a large noise margin between them.

Two states → two voltage levels → maximum noise margin
Boolean algebra (AND/OR/NOT) operates naturally on binary values
Arithmetic (add, subtract, multiply) reduces to simple bit operations

Follow-up: “Why is hex (base-16) used when writing binary values?” — Because 4 bits map directly to 1 hex digit, making long binary strings much more readable. 1010 1111 = 0xAF.

Q2 What is 2’s complement and why is it used for signed integers? Medium

“2’s complement is the trick that lets you subtract by adding — and it means hardware only needs one adder for both addition and subtraction.”

2’s complement represents negative numbers by inverting all bits of the positive value and adding 1. The key advantages:

Single zero: unlike sign-magnitude, there is only one representation of zero
Subtraction by addition: A − B = A + (2’s complement of B). No separate subtractor circuit needed
Overflow detection: carry into MSB ≠ carry out of MSB signals overflow
Range: n-bit 2’s complement covers −2^(n−1) to +2^(n−1) − 1

Example (8-bit): +45 = 0010 1101 → invert → 1101 0010 → +1 → 1101 0011 = −45

Follow-up: “What is −128 in 8-bit 2’s complement?” — 1000 0000. Note: the 2’s complement of 1000 0000 is itself — this is the only asymmetric value in the range.

Q3 Convert 0.625 decimal to binary. Walk me through it. Medium

“For fractions you just keep multiplying by 2 and harvesting the integer part each time.”

The repeated-multiplication-by-2 algorithm:

0.625 × 2 = 1.25 → bit = 1, remainder 0.25
0.25 × 2 = 0.50 → bit = 0, remainder 0.50
0.50 × 2 = 1.00 → bit = 1, remainder 0.00 ✓

Result: 0.101₂

Verify: 0.101₂ = 1×2⁻¹ + 0×2⁻² + 1×2⁻³ = 0.5 + 0 + 0.125 = 0.625 ✓

Follow-up: “Can all decimal fractions be represented exactly in binary?” — No. 0.1 in decimal is a repeating fraction in binary (0.000110011…), just like 1/3 is repeating in decimal. This is why floating-point comparisons like 0.1 + 0.2 == 0.3 can fail.

Q4 What is an overflow condition? Give an example with 4-bit 2’s complement. Medium

“Overflow is when your result is too big or too small to fit in the number of bits you have — you’ve spilled outside the representable range.”

Overflow occurs when two numbers of the same sign are added and the result has the opposite sign. Detection: carry into MSB ≠ carry out of MSB.

4-bit example: +7 + +6 = ?
0111 (+7)
+ 0110 (+6)
─────
1101 ← this is −3 in 2’s complement, not +13 (overflow!)

Carry into MSB = 1, carry out of MSB = 0 → overflow detected ✓

Follow-up: “Can overflow occur when adding numbers of opposite signs?” — Never. If you add a positive and a negative number the result is always between the two operands, so it must fit in range.

📋 Binary Codes

Q5 What is Gray code and where is it used? Easy

“Gray code is the code where only one bit changes between consecutive values — and that’s exactly why we need it for rotary encoders and CDC FIFOs.”

Gray code (also called reflected binary code) has the property that adjacent code words differ by exactly one bit. This is critical in two situations:

Mechanical encoders: When a rotary encoder transitions between positions, multiple bits might change at slightly different times in binary code — causing glitches. Gray code guarantees only one track changes at a time
VLSI CDC FIFOs: Read/write pointers cross clock domains. With binary, multiple bits change simultaneously — metastability can corrupt the pointer to any random value. With Gray code, only 1 bit changes, so the receiving domain reads either the old or new pointer — never a corrupted intermediate

Follow-up: “How do you convert binary to Gray code?” — XOR each bit with the next-higher bit: Gray[i] = Binary[i] XOR Binary[i+1]. MSB is the same: Gray[n-1] = Binary[n-1].

Q6 Why does Excess-3 code have a self-complementing property? Hard

“Because 3 + 6 = 9 — the two ‘excess’ values perfectly mirror each other around 9, so flipping the bits does the 9’s complement arithmetic for you.”

XS-3 encodes digit d as BCD(d) + 3. The 9’s complement of d is (9−d). In XS-3: the code for (9−d) = BCD(9−d)+3 = (9−d+3) = (12−d). In 4 bits: (15−d) = NOT(d+3)+1… but more elegantly, the 1’s complement (bit-flip) of XS-3(d) equals XS-3(9−d). This means to compute the 9’s complement of a decimal digit in XS-3, you simply invert all bits — no addition circuit needed. This makes BCD subtraction in XS-3 very hardware-efficient.

Example: XS-3(4) = 0111. NOT(0111) = 1000 = XS-3(5). 4+5=9 ✓

Follow-up: “Is BCD (8421) self-complementing?” — No. The 9’s complement of a BCD digit requires actual subtraction logic, which is why XS-3 was preferred in early decimal computers.

Q7 What is the minimum number of parity check bits needed to correct single-bit errors in an 8-bit data word? Medium

“Use the Hamming rule — 2 to the r must cover r plus m plus 1. For 8 data bits you need 4 parity bits.”

The Hamming condition for single-error correction: 2^r ≥ r + m + 1, where r = parity bits, m = data bits.

m = 8: try r=3: 2³=8, 3+8+1=12. 8 < 12 ✗
try r=4: 2⁴=16, 4+8+1=13. 16 ≥ 13 ✓

r = 4 parity bits → total codeword = 12 bits

Parity bits are placed at positions 1, 2, 4, 8 (powers of 2). Each covers the set of bit positions where its positional bit is 1 in the binary index.

Follow-up: “What is SECDED?” — Single Error Correct, Double Error Detect. Add one more parity bit (overall parity) to the Hamming code — can correct 1-bit errors and detect but not correct 2-bit errors. Used in ECC RAM.

⚡ Boolean Algebra

Q8 State De Morgan’s theorems and give an example of how you’d use them in circuit design. Easy

“De Morgan is basically ‘break the bar, change the sign’ — flip AND to OR or OR to AND, then complement everything. It’s how you convert between NAND and NOR implementations.”

First: (A+B)’ = A’·B’ — complement of OR = AND of complements
Second: (A·B)’ = A’+B’ — complement of AND = OR of complements

Practical use: NAND gates are universal. Any AND-OR SOP circuit can be converted to a two-level NAND-NAND circuit using De Morgan’s: replace each AND gate with a NAND, then each OR gate with a NAND (since NAND(Ā,B̄) = NOT(Ā·B̄) = A+B by De Morgan). This saves chip area because NAND gates are typically faster and smaller than AND or OR gates in CMOS.

Follow-up: “What is the De Morgan equivalent of an NOR gate?” — NOR(A,B) = NOT(A+B) = A’·B’ by De Morgan. So NOR is equivalent to an AND gate with inverted inputs.

Q9 Why are NAND and NOR called “universal gates”? Easy

“Universal means you can build ANY logic function using only that one gate type — no AND, no OR, no NOT needed separately. The whole chip from just NANDs, if you want.”

NOT from NAND: Connect both inputs together → NAND(A,A) = NOT(A)
AND from NAND: NAND followed by NOT (2 NANDs)
OR from NAND: NOT each input, then NAND → NAND(A’,B’) = A+B (De Morgan)

Since AND, OR, and NOT are functionally complete, and all three can be built from NAND alone, NAND is universal. Same argument applies for NOR. This matters in practice because fab processes are optimised for one gate topology — TTL chips used NAND-heavy designs; CMOS uses a mix but NAND is still preferred (fewer transistors than NOR for equivalent logic).

Follow-up: “Is an AND gate universal on its own?” — No. AND alone cannot produce NOT (you can’t invert with an AND gate). You need complementation for functional completeness.

Q10 What is the difference between SOP and POS forms? When would you prefer one over the other? Medium

“SOP is AND-then-OR — you OR together product terms. POS is OR-then-AND — you AND together sum terms. SOP maps to NAND-NAND; POS maps to NOR-NOR.”

Sum of Products (SOP): F = AB + CD + A’B’C — each term is a minterm or implicant. A 1 in the truth table contributes a term. Maps directly to AND-OR or NAND-NAND two-level logic.

Product of Sums (POS): F = (A+B)(C+D)(A’+B’+C’) — each factor is a maxterm. A 0 in the truth table contributes a factor. Maps to OR-AND or NOR-NOR two-level logic.

When to choose: If the function has more 1s than 0s in the truth table, K-map 0-grouping (POS) gives fewer terms. If more 0s, SOP from 1-grouping wins. In VLSI, NOR-NOR is rarely used because NOR gates in CMOS require P-type transistors in series, which is slower — NAND-NAND (SOP) is almost always preferred.

Follow-up: “Are SOP and POS for the same function always equivalent?” — Yes, they implement the same truth table — just using different algebraic forms. Both give the same outputs for every input combination.

🗺️ K-Map Simplification

Q11 What is a K-map and why does it work for minimising Boolean expressions? Easy

“A K-map is a truth table rearranged so that adjacent cells differ by exactly one variable — it turns algebraic simplification into a visual pattern-spotting exercise.”

The Karnaugh map arranges minterms in a 2D grid using Gray code ordering on both axes. Adjacent cells differ in exactly one variable. When you group adjacent 1s, the differing variable cancels out algebraically (A+A’ = 1), giving a simpler product term. The rules:

Groups must be rectangular with size a power of 2 (1, 2, 4, 8…)
Larger groups → more variables cancel → simpler expression
The map wraps toroidally — top/bottom and left/right edges are adjacent
Don’t-cares can be grouped with 1s to form larger groups
Every 1 must be covered by at least one group

Follow-up: “What is a prime implicant vs an essential prime implicant?” — A prime implicant is the largest possible group covering a set of 1s that cannot be expanded further. An essential prime implicant is one that covers at least one 1 not covered by any other prime implicant — it must be included in the minimal expression.

Q12 How do you handle don’t-care conditions in a K-map? Could they ever hurt you? Medium

“Don’t-cares are free real estate — you assign them 0 or 1 however helps you make bigger groups. But the catch is, if that input combination ever actually shows up, you get undefined behaviour.”

Don’t-care conditions (marked X or d) arise when certain input combinations are guaranteed never to occur (e.g. illegal BCD codes 1010–1111) or when we truly don’t care about the output. Strategy: treat don’t-cares as 1s where they help form a larger group, and as 0s everywhere else.

The risk: If you assume a combination never occurs but your circuit receives it (due to a fault, power-on transient, or design error), the output is unpredictable. In safety-critical designs, don’t-cares are often explicitly driven to a known safe value rather than left truly undefined.

Follow-up: “In VLSI synthesis, how does the tool treat don’t-cares?” — The synthesis tool uses don’t-cares aggressively to minimise area. It assigns them whichever value reduces gate count — similar to how we use them in K-maps. Formal verification tools then check that the real implementation never exercises a don’t-care path in production.

Q13 What is the Quine-McCluskey method and when would you use it over a K-map? Hard

“Q-M is the algorithmic version of K-map — it’s what you use when you have more variables than you can draw on paper, or when you need a computer to do the minimisation.”

Quine-McCluskey is a tabular minimisation algorithm that finds all prime implicants systematically. It works by:

Group minterms by number of 1-bits in their binary representation
Combine adjacent groups that differ in exactly one bit position (the differing bit becomes a dash)
Repeat until no further combining is possible — all remaining terms are prime implicants
Use a prime implicant chart (covering table) to find the minimal cover

K-map vs Q-M: K-map works visually for up to 5–6 variables. Q-M scales to any number of variables and is directly implementable as a computer algorithm — this is what early EDA synthesis tools used. Modern tools use more advanced algorithms (ESPRESSO heuristic), but Q-M is the foundation.

Follow-up: “What is the ESPRESSO algorithm?” — A heuristic minimisation tool that doesn’t guarantee the absolute minimum but finds a very good solution much faster than Q-M for large functions. Used in logic synthesis since the 1980s.

➕ Combinational Circuits

Q14 What is the difference between a half adder and a full adder? Which one does a CPU use? Easy

“Half adder adds two bits, full adder adds three — the extra one being the carry-in from the previous column. CPUs use full adders chained together for multi-bit addition.”

Half Adder: 2 inputs (A, B), 2 outputs (Sum = A⊕B, Carry = A·B). Cannot handle carry-in from a previous stage
Full Adder: 3 inputs (A, B, Carry_in), 2 outputs (Sum = A⊕B⊕Cin, Cout = A·B + (A⊕B)·Cin). Can be chained

A CPU’s ALU uses a chain of full adders (ripple-carry or carry-lookahead). The LSB stage can be a half adder (Cin = 0) and all subsequent stages are full adders. In practice, VLSI CPUs use carry-lookahead adders (CLA) or Kogge-Stone adders to avoid the O(n) ripple delay.

Follow-up: “What is the maximum carry propagation delay in a 64-bit ripple-carry adder at 10ns per full adder?” — 64 × 10ns = 640ns. This is why CPUs don’t use ripple-carry — modern 64-bit adders use Kogge-Stone or Han-Carlson trees to reduce this to O(log n) ≈ 6 stages.

Q15 Explain how a 2’s complement adder/subtractor works using a single circuit. Medium

“You use XOR gates as controlled inverters — when the SUB signal is 0 they pass B unchanged, when it’s 1 they flip all the bits. Then you connect SUB directly to carry-in so it adds 1 automatically. Boom — 2’s complement subtraction.”

The circuit uses B XOR SUB for each bit and connects SUB to carry-in (C₀):

SUB = 0 (Addition): B⊕0 = B (unchanged). C₀ = 0. Result: A + B
SUB = 1 (Subtraction): B⊕1 = B̄ (bitwise NOT = 1’s complement). C₀ = 1. Result: A + B̄ + 1 = A + (2’s complement of B) = A − B

This is the core of every ALU — one adder circuit handles both operations. The XOR gate acts as a programmable inverter: A XOR 0 = A (pass through), A XOR 1 = A' (invert).

Follow-up: “How does the CPU detect overflow after subtraction?” — Carry out of MSB ≠ carry into MSB. In hardware, COUT⊕(carry into MSB) sets the overflow flag in the status register.

Q16 Why does a BCD adder need correction logic and what does it add? Medium

“BCD only uses 0–9, but a binary adder can produce 0–15. The illegal codes 10–15 need to be fixed by adding 6 — because 6 is the gap between 10 (decimal) and 16 (the next power of 2).”

A standard 4-bit binary adder can produce results from 0 to 15 (0000 to 1111). BCD only allows 0000 to 1001 (0–9). When the sum falls in the illegal range 1010–1111 (10–15), correction is needed:

Add 0110 (6) to skip the six illegal codes
Adding 6 to 10 gives 16 = 10000, which means carry out = 1 and remainder = 0 — correct BCD result

Correction detect logic: X = S₄ + S₃·S₂ + S₃·S₁, where S₄S₃S₂S₁S₀ is the 5-bit binary sum. X = 1 means correction is needed.

Follow-up: “How many adder stages does a single-digit BCD adder require?” — Two: the first stage is a standard 4-bit binary adder. The second stage adds 0110 only when X = 1. Two 74LS83 ICs plus correction gates implement this in hardware.

🔀 MUX, Decoders & PLDs

Q17 How can a MUX be used to implement any Boolean function? Why is this powerful? Medium

“A 2^n :1 MUX with n select lines can implement any Boolean function of n variables — just wire each data input to 0 or 1 based on the truth table. It’s a hardware lookup table.”

Connect the n input variables to the select lines. For each of the 2^n combinations, the corresponding data input Xᵢ is set to the function’s output value for that combination:

Xᵢ = 1 if F = 1 for minterm i
Xᵢ = 0 if F = 0 for minterm i

Reduced MUX method: Use a 2^(n-1):1 MUX for an n-variable function by assigning the MSB variable to the data inputs (each input can be 0, 1, MSB, or MSB’). This halves the MUX size. In VLSI/FPGAs, this is exactly what a LUT (Look-Up Table) does — a 4-input LUT is a 16:1 MUX with its inputs hardwired to implement any 4-variable function.

Follow-up: “What is the difference between how MUX and PROM implement Boolean functions?” — Both are lookup tables, but MUX outputs one function (with data inputs wired to 0/1), while PROM can implement multiple functions simultaneously — each output bit is a separate function of the same input address.

Q18 What is the difference between a FPLA, PAL, and PROM? When would you choose each? Hard

“These are three different tradeoffs between flexibility and simplicity. FPLA is fully flexible but complex to program. PAL is simpler and faster. PROM gives you all minterms but wastes AND-plane silicon.”

FPLA (Field Programmable Logic Array): Both AND array and OR array programmable. Maximum flexibility — any SOP expression. Harder to program and test. Used when the OR terms need to be shared across multiple outputs.
PAL (Programmable Array Logic): AND array programmable, OR array fixed. Each output has a fixed set of AND gates feeding it. Simpler to design and faster — OR plane is just metal connections, no programming fuses. The most common PLD type for SOP logic.
PROM: AND array fixed (all 2^n minterms always present), OR array programmable. Perfect for truth-table-based functions, code conversion, and look-up tables. Wastes silicon if only a few minterms are used.

Follow-up: “Are these used in modern design?” — PLDs evolved into CPLDs and FPGAs. CPLDs are essentially large PAL-like structures. FPGAs use SRAM-based LUTs instead of fusible links. The programming concepts (AND/OR arrays, look-up tables) are still directly applicable.

Q19 How do you build a 4-to-16 decoder from two 3-to-8 decoders? Medium

“Use the 4th address bit to steer between the two decoders — connect it through a NOT gate to the enable of one decoder and directly to the enable of the other.”

The MSB (A₃) selects which decoder is active:

Decoder 1 (outputs Y₀–Y₇): Enable connected to A₃’ (active when A₃=0)
Decoder 2 (outputs Y₈–Y₁₅): Enable connected to A₃ (active when A₃=1)
Both decoders share the same lower 3 address lines A₂A₁A₀

When A₃=0: Decoder 1 is enabled and outputs Y₀–Y₇ based on A₂A₁A₀. Decoder 2 is disabled (all outputs 0). When A₃=1: Decoder 2 is enabled and outputs Y₈–Y₁₅. This extends to larger decoders recursively — 5-to-32 from two 4-to-16, etc.

Follow-up: “How many gates minimum does this need beyond the two decoders?” — Just one NOT gate (for A₃’). The enables are the key — active-low enable decoders need slightly different connections.

Q20 What is the propagation delay hazard in combinational circuits and how do you fix it? Hard

“A hazard is a glitch — a momentary wrong output while the circuit is settling after an input change. Static hazards come from K-map groups that don’t overlap; you fix them by adding a redundant consensus term.”

A static-1 hazard occurs when the output should remain at 1 but glitches to 0 momentarily during a transition. It happens when two adjacent K-map groups have a gap — as the circuit switches from one prime implicant to another, neither is momentarily asserting the output.

Fix: Add the consensus term — a redundant prime implicant that bridges the gap between the two groups. This overlapping term keeps the output high during the transition.

Dynamic hazard: Output changes more than once when it should change exactly once. Occurs in multi-level circuits. Fix: reduce to two-level logic.

Follow-up: “Are hazards a problem in synchronous digital design?” — Generally no. Synchronous designs only sample outputs at the clock edge, long after all transients have settled. Hazards become a problem in asynchronous circuits where glitches can trigger spurious state transitions.

Post 2 coming up: Logic Families, Flip-Flops, Shift Registers, Counters, DAC/ADC, and Digital Memories — the hardware-heavy and sequential circuit questions that dominate VLSI and embedded systems interviews.

↑ DE Series Index Interview Q&A Post 2 — Logic Families & Sequential →