DAC & ADC – Your VLSI Journey Starts Here

🌉 The Analog–Digital Interface

The real world is analog — temperature, pressure, sound, light, and voltage are all continuous quantities. Digital processors work exclusively with binary numbers. DAC and ADC are the bridge between these two domains.

Figure 1 — Complete signal chain. An ADC digitises an analog sensor output for processing. After processing, a DAC reconstructs the analog output to drive an actuator. In VLSI SoCs, both ADC and DAC are integrated on-chip alongside the digital processor.

⚖️ Weighted Resistor DAC

The simplest DAC uses a resistor network where each bit’s resistor is half the value of the next lower-significant bit’s resistor. Each bit drives VREF or 0V through its resistor. A summing op-amp adds the weighted currents.

For an n-bit weighted-resistor DAC with feedback resistor Rƒ:

V_out = −(V_REF / 2^(n−1) · R) · [2⁰·b₀ + 2¹·b₁ + 2²·b₂ + … + 2^(n−1)·b_(n−1)]

Each bit bᵢ = 0 or 1 (connects its resistor to GND or V_REF). The output is proportional to the binary code.

Example 11.1 — 6-bit weighted DAC: input 110110, V_REF = 10V

Bitsb₅=1, b₄=1, b₃=0, b₂=1, b₁=1, b₀=0 → decimal weight = 32+16+0+4+2+0 = 54

FormulaV_L = (V_REF / 63) × (b₀×1 + b₁×2 + b₂×4 + b₃×8 + b₄×16 + b₅×32)

CalculateV_L = (10/63) × 54 = 540/63

V_out = 8.57 V

Drawbacks of Weighted Resistor DAC

Wide resistor range — for a 10-bit DAC, resistors span a ratio of 2⁹ = 512:1 (e.g. 1 kΩ to 512 kΩ). Precision resistors across this range are difficult to match and temperature-track.
Current imbalance — the LSB current source is 2^(n−1) times smaller than the MSB. In a 10-bit DAC, LSB current ≈ 512× smaller, affecting linearity.

🔗 R-2R Ladder DAC

The R-2R ladder solves the precision problem by using only two resistor values — R and 2R — regardless of the number of bits. The ratio R:2R is all that matters, and this ratio can be maintained accurately in silicon (both resistors track each other with temperature).

Figure 2 — R-2R ladder DAC. Looking into any node, the Thevenin resistance is always R — the ladder is self-similar. Each bit switch connects its 2R resistor to either V_REF (bit=1) or GND (bit=0). The MSB contributes V_REF/2, each subsequent bit contributes half the previous.

General output formula for n-bit R-2R ladder DAC:

V_out = −(V_REF / 2ⁿ) × [2⁰·b₀ + 2¹·b₁ + 2²·b₂ + … + 2^(n−1)·b_(n−1)]

Example 11.3 — 5-bit R-2R Ladder DAC, input 10110, V_REF = 10V

Weightsb₄=1→16, b₃=0→0, b₂=1→4, b₁=1→2, b₀=0→0 → sum = 22

FormulaV_out = −(10/32) × 22 = −220/32

V_out = −6.875 V

Why R-2R dominates in VLSI. The R-2R network uses only two resistor values — both can be laid out as multiples of a unit resistor in a matched array. In CMOS DAC design, these resistors track each other across process, voltage, and temperature (PVT) variations, giving excellent linearity. The bit switches are CMOS transmission gates driven directly by the digital input bits.

📊 DAC Performance Criteria

Parameter	Definition	Formula / Example	VLSI significance
Resolution	Smallest change in output per 1 LSB change in input (step size)	Step = V_FS / (2ⁿ − 1) e.g. 10V/1023 ≈ 9.78 mV for 10-bit	Determines the granularity of D/A conversion — higher bits = finer steps
Accuracy	Maximum deviation of actual output from ideal straight line (% of full scale)	8-bit: accuracy ≤ ±0.2% (±½ LSB)	Determines absolute correctness — affected by resistor mismatch, op-amp offset
Monotonicity	Analog output increases strictly when digital input increases (staircase has no downward steps)	If any step is negative, converter is non-monotonic → defective or poorly designed	Critical for control systems — non-monotonic DAC causes oscillation in feedback loops
Settling time	Time for output to settle within ±½ LSB of final value after input change	Typical: 100 ns to 10 μs depending on DAC architecture	Limits how fast the DAC can update — determines maximum output sample rate

Example 11.4 — Resolution of 12-bit DAC, 10V full scale

Step size10V / (2¹² − 1) = 10 / 4095 = 2.44 mV

% Resolution1 / 4095 × 100 = 0.0244%

Step size = 2.44 mV Resolution = 0.0244%

Example 11.5 — Bits needed for 10 mV resolution, 10V full scale

Setup10 mV = 10V / (2ⁿ − 1) → 2ⁿ − 1 = 1000 → 2ⁿ ≈ 1001

Solve2¹⁰ = 1024 > 1001 → n = 10 bits sufficient

10 bits required for 10 mV resolution with 10V full scale

🔌 IC DAC0808 — 8-bit Current-Output DAC

The DAC0808 (also DAC0800) is a popular 8-bit R-2R ladder DAC with internal transistor switches. It outputs a current proportional to the 8-bit input, which is converted to voltage by an external op-amp.

Parameter	Value
Resolution	8-bit (256 steps)
Output type	Current (I_out); external op-amp converts to voltage
Reference current	2 mA (set by +5V → R_ref)
Output range	0 to −2 mA (approx 0 to 2V with 1 kΩ feedback)
Supply	+5V (pin 13) and −15V (pin 3 = V_CC)
Input pins	Pins 5–12: digital inputs b₁ (MSB) to b₈ (LSB)
Settling time	~150 ns
Package	DIP-16

Using DAC0808. Connect a +5V reference through a resistor to pin 15 to set the reference current. Pin 4 (I_out) connects to the inverting input of an op-amp with feedback resistor R_f. The output voltage V_out = −I_out × R_f. For 0–5V range with R_f = 2.5 kΩ: V_out = 0V (input 0x00) to −5V (input 0xFF).

⚡ Flash (Simultaneous) ADC

The flash ADC is the fastest conversion method — all bits are resolved in a single clock cycle. For an n-bit output, it requires 2ⁿ − 1 comparators in parallel, each comparing the analog input against evenly spaced reference voltages. A priority encoder then converts the thermometer-code comparator outputs into binary.

Figure 3 — 3-bit flash ADC. Seven comparators (2³−1) compare V_in against evenly spaced references. Comparators with V_ref < V_in output HIGH (thermometer code). The priority encoder converts the thermometer code to 3-bit binary. Entire conversion in one comparator delay + one encoder delay.

🎯 Successive Approximation (SAR) ADC

The SAR ADC determines each bit sequentially from MSB to LSB — like a binary search. It requires exactly n clock cycles for n-bit conversion and needs only one comparator and one DAC.

Figure 4 — SAR conversion of 6V in 4 clock cycles. Each cycle the SAR tries the next bit = 1. If V_DAC > V_in, that bit is cleared; otherwise kept. After n cycles the SAR register holds the n-bit digital code.

🔬 SAR ADC dominates VLSI. The SAR architecture is the most widely used ADC in modern VLSI/SoC designs — it achieves an excellent trade-off of speed (n clock cycles), power (one comparator, one DAC), and resolution (12–18 bits achievable). Almost every microcontroller, IoT chip, and mixed-signal SoC uses a SAR ADC for its on-chip A/D function. The key VLSI challenge is the internal DAC — it must be monotonic and settle within one clock period.

📈 Counter-Ramp ADC

A binary counter drives a DAC to generate a staircase ramp. The counter increments each clock until the DAC output equals or exceeds V_in. The counter value at that moment is the digital output. Simple but very slow — maximum conversion time is 2ⁿ clock cycles (for full-scale input). Only suitable for very slowly changing signals.

Modified version (tracking ADC): Use an up/down counter instead of resetting each cycle. The counter tracks V_in by incrementing when DAC < V_in and decrementing when DAC > V_in. Faster for slowly varying signals, oscillates by ±1 LSB around V_in in steady state.

📐 Dual-Slope ADC

The dual-slope ADC offers excellent noise rejection and accuracy but low speed. It integrates V_in for a fixed time t₁, then integrates −V_REF until the output returns to zero. The time t₂ for the second phase is proportional to V_in:

V_in = V_REF × (t₂ / t₁)

The key advantage: the conversion result depends only on the ratio of times t₂/t₁ and the ratio V_REF — not on the values of R and C. Component variations do not affect accuracy. Also, integrating over a full period of 50/60 Hz power line frequency cancels power-line noise — making dual-slope ideal for digital multimeters and precision instruments.

Phase	Switch position	Duration	Integrator output
Phase 1 (charge)	V_in connected	Fixed t₁ (set by counter overflow)	Ramps down by V_in × t₁ / RC
Phase 2 (discharge)	−V_REF connected	Variable t₂ until output = 0	Ramps back up to 0
Result	—	Counter counts t₂ → digital output	Count ∝ V_in × (t₁/t₂) / V_REF

Dual-slope in VLSI context. Dual-slope ADCs appear in precision mixed-signal ICs for measurement applications (digital multimeters, weighing scales, precision temperature sensors). Conversion time is slow (tens of milliseconds) but accuracy can reach 18–24 bits. Modern Sigma-Delta (ΔΣ) ADCs achieve comparable accuracy at much higher speeds — ΔΣ has largely replaced dual-slope in high-resolution VLSI applications, using oversampling and noise-shaping rather than two-ramp integration.

🔌 IC ADC0801 — 8-bit SAR ADC

The ADC0801 is a popular 8-bit successive approximation ADC in a 20-pin DIP. It contains an on-chip clock generator (external R and C set the frequency), SAR logic, R-2R DAC, and comparator.

Pin	Name	Function
1	C̄S̄	Chip select (active-low)
2	R̄D̄	Output enable (active-low) — digital outputs float when high
3	W̄R̄	Start conversion (active-low pulse)
4	CLK IN	External clock or RC oscillator node (connect C here)
5	INTR̄	Interrupt — goes low when conversion complete
6	V_IN(+)	Non-inverting analog input
7	V_IN(−)	Inverting analog input (differential; tie to AGND for single-ended)
9	V_REF/2	Half of reference voltage (leaves floating for 0–5V range)
11–18	D₇–D₀	8-bit digital output (tri-state — active only when C̄S̄ and R̄D̄ both low)
19	CLK R	Resistor connection for internal RC clock
20	V_CC	+5V supply

Clock frequency: f = 1 / (1.1 × R × C) — should be in range 100 kHz to 800 kHz. Conversion time = 8/f_CLK ≈ 100 μs at 640 kHz clock. Tri-state outputs: C̄S̄=0 AND R̄D̄=0 to read output; otherwise pins float (bus-friendly).

⚖️ ADC Comparison — Speed vs Accuracy vs Hardware

Architecture	Conversion time	Hardware	Accuracy	Best for
Flash	1 clock cycle	2ⁿ−1 comparators (exponential!)	6–8 bit typical	Ultra-high speed: video, radar, oscilloscopes
SAR	n clock cycles	1 comparator + 1 DAC + SAR register	8–18 bit	General purpose: microcontrollers, sensors, audio
Counter-ramp	Up to 2ⁿ clock cycles	1 comparator + 1 counter + 1 DAC	8–12 bit	Slow/educational; rarely used in practice
Single-slope	Proportional to V_in	Integrator + 1 comparator + counter	Moderate (R,C dependent)	Simple, slow measurements
Dual-slope	~2 × 2ⁿ clocks (ms range)	Integrator + 1 comparator + counter	High (R,C independent)	Precision: DMMs, scales, temperature
Sigma-Delta (ΔΣ)*	Many cycles (oversampled)	1-bit modulator + digital filter	16–24 bit	Audio, precision measurement, modern VLSI

* Sigma-Delta is beyond this textbook’s scope but is the dominant architecture in modern VLSI mixed-signal design.

🔬 VLSI Mixed-Signal Perspective

Where DACs and ADCs live in VLSI SoCs.

On-chip ADC — Almost every MCU and SoC integrates a 10–12 bit SAR ADC for general-purpose analog-to-digital conversion of sensor signals, battery monitoring, and temperature sensing. The key design challenge is preventing digital switching noise from coupling into the sensitive analog comparator and reference circuits — requiring careful floorplanning, dedicated analog power rails, and guard rings.
On-chip DAC — R-2R DACs appear in microcontrollers for PWM-smooth analog output, in sigma-delta ADCs as the internal 1-bit DAC, and in PLLs as charge pumps. Audio SoCs use high-resolution (24-bit) pipeline DACs with low-distortion output stages.
Reference voltage (V_REF) — The accuracy of any DAC or ADC is limited by the accuracy of V_REF. On-chip bandgap references provide a temperature-stable ~1.2V reference — accurate to within 0.1–1% over temperature without trimming, and better with laser-trim calibration.
Sample-and-hold (S&H) — Every ADC needs a sample-and-hold circuit at the input to freeze V_in during conversion. At high sampling rates, the aperture jitter of the S&H switch becomes the dominant noise source — a key concern for RF ADCs sampling at GHz rates.
Nyquist theorem — The sampling rate must be at least 2× the highest signal frequency (f_s ≥ 2 × f_max) to avoid aliasing. In practice, a factor of 2.5–3× is used, with an anti-aliasing filter before the ADC to band-limit the input.

📋 Quick Reference

DAC type	Resistors	Formula	Advantage
Weighted resistor	n different values: R, 2R, 4R… 2^(n-1)R	V_L = V_REF/(2ⁿ−1) × Σ(2ⁱ·bᵢ)	Simple; few components
R-2R ladder	Only R and 2R (2 values)	V_out = −V_REF/2ⁿ × Σ(2ⁱ·bᵢ)	Precision; VLSI-friendly; preferred

DAC parameter	Formula
Step size (resolution in V)	V_FS / (2ⁿ − 1)
% Resolution	1/(2ⁿ − 1) × 100
Bits for given step size	2ⁿ − 1 = V_FS / step; solve for n

ADC	Speed	Comparators	IC example
Flash	1 cycle	2ⁿ−1	—
SAR	n cycles	1	ADC0801 (8-bit)
Counter-ramp	≤2ⁿ cycles	1	—
Dual-slope	~2×2ⁿ cycles	1	ICL7107 (DMM IC)

Coming next — DE-12: Digital Memories — ROM, PROM, EPROM, EEPROM semiconductor memories — SRAM, DRAM, and their cell structures — ROM applications (logic functions, look-up tables, code converters) — Magnetic disk and optical memory — Memory parameters: access time, cycle time, volatile vs non-volatile, destructive readout.

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