Asynchronous ripple counters, synchronous binary counters, up/down counters, Mod-N design procedure, decade counters, arbitrary-sequence counters, counter ICs (7490, 7492, 7493, 74160, 74163, 74190) — and their role in VLSI clock dividers, scan chains, and timing control.
🔢 Counter Basics & VLSI Relevance
A counter is a sequential circuit that advances through a defined sequence of states on each clock edge. The total number of unique states is the counter’s modulus (Mod-N). An n-bit binary counter has modulus 2ⁿ.
🔬 VLSI perspective. Counters are fundamental to VLSI design at every level:
Clock dividers — a T flip-flop chain divides f_CLK by powers of 2; PLLs use programmable counters for fractional division
Timing state machines — finite state machines in VLSI are often implemented as encoded counters
Gray code counters — used in CDC (clock domain crossing) FIFOs to avoid metastability when pointer crosses clock domains
Type
Clock
Propagation delay
Max frequency
VLSI use
Asynchronous (ripple)
Only FF₀ gets external CLK; each FF clocked by previous Q
Accumulates — n × t_pd
Low (limited by n)
Simple clock dividers, low-speed
Synchronous
All FFs share the same clock
Fixed — t_pd of one FF + combinational logic
High (independent of n)
All high-speed VLSI counters, address generators, scan
🌊 Asynchronous (Ripple) Counters
In a ripple counter, a T flip-flop toggles on every falling edge of its input. The output of each FF drives the clock of the next. A single T flip-flop with T=1 permanently connected divides the input frequency by 2:
Figure 1 — 4-bit ripple counter. Each FF is clocked by the Q output of the previous FF. Each stage divides the frequency by 2. The total delay from CLK edge to valid Q₃ = 4 × t_pd — this accumulation is the “ripple delay” that limits maximum operating frequency.
Glitch hazard in ripple counters. Because FFs change at different times, intermediate states appear at the output during transitions. For example, transitioning from 0111 (7) to 1000 (8) passes through 0110, 0100, 0000 momentarily before settling. Any combinational logic decoding the counter output must account for these glitches — a key reason synchronous counters are preferred in VLSI designs.
A binary down counter counts in reverse: 15→14→…→1→0→15→… The change: instead of each FF being clocked by Q of the previous FF, it is clocked by Q̄ (complement output). Q̄ goes LOW when Q goes HIGH — so Q̄’s falling edge occurs when Q transitions 0→1, which is the correct trigger for down-counting.
An up/down counter uses multiplexers or AND-OR gates to select whether each subsequent FF is clocked by Q or Q̄ of the previous stage, under control of an UP/DOWN̄ signal.
🔟 Decade (Mod-10) Ripple Counter
A decade counter counts 0–9 and resets on state 10. Since a 4-bit counter naturally counts to 15, states 10–15 must be forced back to 0. The trick: detect state 10 (1010) and use it to immediately RESET all flip-flops via their CLR̄ inputs.
DetectNAND(Q₃, Q₁) — when both HIGH (state 10), NAND output goes LOW
ConnectNAND output → CLR̄ of all 4 flip-flops → immediately resets counter to 0000
ResultState 10 is a transient — it appears for nanoseconds then counter jumps to 0. Valid states: 0–9 only.
Reset condition: NAND(Q₃, Q₁) = 0 at state 10 → CLR̄ = 0 → all FFs reset
Count
Q₃
Q₂
Q₁
Q₀
Action
0–9
Normal counting
Count advances normally
10
1
0
1
0
NAND(Q₃,Q₁)=0 → CLR̄ active → immediate reset to 0000
0
0
0
0
0
Counting resumes
⚙️ Arbitrary Mod-N Ripple Counter
To build any Mod-N counter using ripple flip-flops:
Find the smallest n such that 2ⁿ ≥ N. Use n flip-flops.
Write N in binary.
Connect a NAND gate to the Q outputs of the bits that are 1 in the binary representation of N.
Feed the NAND output to CLR̄ of all flip-flops.
Design Mod-12 ripple counter using 4 T flip-flops
n = 42⁴ = 16 ≥ 12 ✓
12 in binary12 = 1100 → Q₃=1, Q₂=1, Q₁=0, Q₀=0
NAND gateNAND(Q₃, Q₂) → when state 1100 reached, NAND goes LOW → CLR̄ resets all
Mod-12: 4 T flip-flops + NAND(Q₃, Q₂) → CLR̄. Valid states: 0000 to 1011 (0–11).
⚡ Synchronous Counters
All flip-flops in a synchronous counter share the same clock. The flip-flop inputs (J,K or T) are driven by combinational logic derived from the current state. All outputs change simultaneously — no ripple delay, no glitches during transitions.
VLSI standard. Every VLSI counter (in RTL design, FPGAs, standard cell libraries) is synchronous. Asynchronous counters are never used inside a synchronous design because combinational logic cannot safely decode glitchy ripple outputs. The only acceptable use of asynchronous division is at the clock input to a local clock domain buffer — even then the clock is isolated and the divided output is re-synchronised.
Figure 2 — Synchronous vs asynchronous counters. In synchronous counters the propagation delay is a constant (one FF delay plus combinational logic delay) regardless of the number of bits — making synchronous counters suitable for all high-speed VLSI designs.
📐 Synchronous Counter Design Procedure
Determine number of flip-flops: n such that 2ⁿ ≥ Mod-N.
Draw the state table: list all valid states (present state → next state) with don’t-care conditions for unused states.
Build excitation table: for each flip-flop, determine the required J,K (or T or D) inputs for each state transition using the FF excitation table.
Minimise with K-map: derive minimal Boolean expression for each FF input in terms of current state outputs Q₀, Q₁, Q₂…
Draw combinational input logic: AND-OR gates (or NAND-NAND) implementing the minimised expressions, feeding into the FF inputs.
Design Synchronous Mod-8 Counter using T flip-flops
This is the same as the ripple counter but implemented synchronously — the combinational AND gate ensures Q₂ toggles only when the correct condition is met, on the same clock edge as all other FFs.
Design Synchronous Mod-8 Counter using JK flip-flops (from K-map)
J₀, K₀Toggle every clock: J₀ = K₀ = 1
J₁, K₁Toggle when Q₀=1: J₁ = K₁ = Q₀
J₂, K₂Toggle when Q₁=1 AND Q₀=1: J₂ = K₂ = Q₁·Q₀
J₀=K₀=1 J₁=K₁=Q₀ J₂=K₂=Q₁·Q₀
General pattern for synchronous binary UP counter (any width): T₀ = 1; T₁ = Q₀; T₂ = Q₁·Q₀; T₃ = Q₂·Q₁·Q₀; … Tₙ = Q(n-1)·…·Q₁·Q₀. Each stage’s T input is the AND of all lower-order Q outputs — this is the “carry” logic, and in hardware it forms a carry chain identical to a parallel binary adder.
🔟 Synchronous Decade Counter
A synchronous Mod-10 counter must return from state 9 (1001) to state 0 (0000) on the next clock. The state transition 1001 → 0000 requires specific J,K inputs for each FF — derived from the excitation table and K-map minimisation.
State
Q₃Q₂Q₁Q₀
Next state
J₃ K₃
J₂ K₂
J₁ K₁
J₀ K₀
0
0000
0001
0 φ
0 φ
0 φ
1 φ
1
0001
0010
0 φ
0 φ
1 φ
φ 1
4
0100
0101
0 φ
φ 0
0 φ
1 φ
8
1000
1001
φ 0
0 φ
0 φ
1 φ
9
1001
0000
φ 1
0 φ
0 φ
φ 1
After K-map minimisation of all J,K inputs across all 10 states (with states 10–15 as don’t-cares), the minimal expressions are:
A synchronous up/down counter uses a control input S: S=1 → count up; S=0 → count down. The T flip-flop inputs are derived from K-map minimisation of the combined up and down state tables.
For a Mod-8 synchronous up/down counter using T flip-flops:
T₀ = 1 T₁ = Q₀·S + Q̄₀·S̄ (= Q₀ when S=1, Q̄₀ when S=0) T₂ = Q₁·Q₀·S + Q̄₁·Q̄₀·S̄
VLSI up/down counter design insight. The up path uses AND(Q(n-1), …, Q₀) and the down path uses AND(Q̄(n-1), …, Q̄₀). A MUX (controlled by UP/DOWN̄) selects which term feeds each FF’s toggle input. In RTL synthesis this maps directly to a standard-cell MUX in front of a D-FF with enable.
🎮 Controlled and Arbitrary-Sequence Counters
A controlled counter switches between two different moduli based on a control input. Example: count Mod-4 when S=0, Mod-8 when S=1 — the same flip-flops, different J,K logic.
An arbitrary-sequence counter counts in any user-defined order — e.g. Gray code (0,1,3,2,6,7,5,4), or BCD excess-3 code. The design uses the same 5-step procedure, with the required next-state sequence defining the state table.
🔬 Gray-code counters in VLSI. In asynchronous FIFO design (critical in VLSI SoC clock-domain crossing), the read and write pointers are implemented as Gray-code counters. Gray code ensures only one bit changes per clock cycle — when the pointer value is passed across a clock domain boundary, metastability affects at most one bit, making the received value either the old or new pointer with no intermediate corrupted states.
Synchronous LOAD (preset to any BCD); synchronous CLEAR; Carry Out (CO) HIGH at count 9; enable pins FE1, FE2
CO of stage N → FE1,FE2 of stage N+1
74163
Synchronous 4-bit binary counter
Same as 74160 but counts 0–15; CO HIGH at count 15 (1111); synchronous clear
CO of stage N → FE1,FE2 of stage N+1
74190
Synchronous up/down decade counter
UP/DOWN̄ control (BA pin); synchronous LOAD; pin U pulses at terminal count; bidirectional
U output of stage N → enable of stage N+1
74191
Synchronous up/down 4-bit binary
Same as 74190 but MOD-16
Same cascade method
Cascading synchronous counters. Connect the Carry Out (CO) or Terminal Count (TC) of the lower stage to the Count Enable (CE or FE) of the higher stage. All stages share the same clock. The CO pulse is ONE clock cycle wide and is generated synchronously — no glitches. This allows 8-bit (two 74163s), 12-bit, 16-bit or larger synchronous counters without any asynchronous hazards.
🛠️ Applications
Digital Clock
A digital clock needs three counter stages: seconds (÷60), minutes (÷60), hours (÷12 or ÷24). Each ÷60 is built from a ÷10 counter (7490 in BCD mode) cascaded with a ÷6 counter (7490 in ÷5 mode with the MSB). The output of each stage drives a BCD-to-7-segment decoder (7447) and an FND display. A 1 Hz reference from a 32.768 kHz crystal oscillator divided by 2¹⁵ provides the 1 Hz tick.
Digital Frequency Meter
The unknown frequency is shaped into a pulse train via Schmitt trigger. A 1-second gate pulse (from a precise 1 Hz oscillator) opens an AND gate, passing the pulse train to a counter for exactly 1 second. The count displayed = frequency in Hz. For kHz display: use 1 ms gate; for MHz: use 1 μs gate.
Accuracy depends entirely on gate pulse precision → derived from a temperature-controlled crystal oscillator (TCXO) or GPS-disciplined reference in precision instruments.
Parallel-to-Serial Conversion via Counter + MUX
Connect the outputs of a Mod-N counter to the select inputs of an N:1 MUX. The parallel data connects to MUX data inputs. Each clock cycle the counter increments the select value, routing successive data bits to the MUX output — implementing parallel-to-serial conversion without a shift register. Widely used in display multiplexing and data serialisers.
🔬 VLSI application — Scan chain length counter. In DFT (Design for Testability), scan chains have a fixed length. A down-counter loaded with the scan chain length counts down during shift mode, asserting a “done” signal when it reaches zero. This counter is synthesised as a standard-cell synchronous counter and is part of the BIST (Built-In Self-Test) controller in every production VLSI chip.
📋 Quick Reference
Counter type
n FFs
Delay
Glitch-free?
Max freq
Ripple (async)
⌈log₂N⌉
n × t_pd
No
1/(n·t_pd)
Synchronous
⌈log₂N⌉
t_pd + t_comb
Yes
1/(t_pd + t_comb)
Design step
For T-FF counter
For JK-FF counter
1. State table
List all Q(n) → Q(n+1) transitions for the required count sequence
2. Excitation table
T = Q(n) ⊕ Q(n+1)
From JK excitation table (DE-08)
3. K-map
Minimise each FF input expression vs all state variables + control inputs
4. Implement
AND-OR logic driving FF inputs; all FFs share common CLK
IC
Modulus
Type
CO/cascade pin
7490
÷10 (BCD)
Async
Q₃ → CLK1 of next
7493
÷16
Async
Q₀ → CLK1; Q₃ to next CLK
74160
÷10
Sync
CO → FE1,FE2 of next
74163
÷16
Sync
CO → FE1,FE2 of next
74190
÷10 up/dn
Sync
U pin → enable of next
Coming next — DE-11: DAC & ADC — Weighted resistor DAC, R-2R ladder DAC, DAC performance criteria (resolution, accuracy, settling time), IC DAC0808 — Flash/simultaneous ADC, Successive Approximation ADC (SAR), Counter-ramp ADC, Dual-slope ADC, and IC ADC0801 — with VLSI converter design perspective.