Computer Internal Memory: Characteristics, Access Methods and Hierarchy

💾Memory Characteristics Overview

A computer’s memory system is not a single uniform thing — it is a carefully engineered hierarchy of different storage technologies, each making different trade-offs between speed, capacity, cost, and persistence. Understanding these trade-offs is fundamental to understanding why computers are designed the way they are.

Every memory system can be characterised along six dimensions:

Characteristic	Options
Location	CPU internal (registers), internal/main (RAM, ROM, cache), external/secondary (disk, tape, optical)
Capacity	Word size (natural unit of the CPU), number of addressable words or bytes
Unit of Transfer	Word (for main memory), block (for secondary storage — e.g. 512-byte disk sector or 64-byte cache line)
Access Method	Sequential, direct, random, associative — see Section S3
Performance	Access time, cycle time, transfer rate
Physical Type	Semiconductor (SRAM, DRAM, Flash), magnetic surface (HDD, tape), optical (CD, DVD, Blu-ray)
Physical Characteristics	Volatile/non-volatile, erasable/non-erasable

📐Location & Capacity

Memory location

CPU-internal (registers): Built directly into the CPU die. Fastest access (~0 cycles). Small — typically 16–256 registers, each one word wide.
Internal/main memory: RAM and ROM chips on the motherboard, connected to the CPU via the memory bus. Addressable by the programmer. Typical size: GBs. Access time: tens to hundreds of nanoseconds.
External/secondary storage: Magnetic disk, SSD, tape. Non-volatile. Addressable via file system. Capacity: GBs to TBs. Access time: milliseconds (HDD) or microseconds (SSD).

Capacity terminology

Word: The natural unit of memory organisation — equal to the number of bits the CPU processes as one unit (typically 8, 16, 32, or 64 bits).
Number of words: Total storage = word size × number of words. A 32-bit processor with a 32-bit address bus can address 2³² = 4 GB of memory.

🔍 Worked Example — Address space calculation

Given: A CPU has a 24-bit address bus and 8-bit (byte) addressable memory.

Addressable locations: 2²⁴ = 16,777,216 = 16 MB

Given: A 16 Mbit DRAM chip, organised as 1M × 16-bit words.

Chip capacity: 1,048,576 locations × 16 bits = 16,777,216 bits = 16 Mbits ✓

Address pins needed: log₂(1,048,576) = 20 address pins. DRAM uses row/column multiplexing — 10 multiplexed pins select row, same 10 pins reused to select column: 2¹⁰ × 2¹⁰ = 1M locations.

🔍Access Methods

The most fundamental distinction between memory types is how data is accessed — how the hardware reaches a specific stored value:

Figure 1 — Four memory access methods compared

Four memory access methods. Sequential (tape) and direct (disk) have variable access times. Random access (DRAM, SRAM) achieves constant access time — any address is reached in the same time. Associative access (CAM) compares a tag against all stored values simultaneously — used in cache tag arrays and TLBs.

⚡Performance Parameters

Parameter	Definition	Applies to	Typical values
Access Time	Time from address presented to data available (RAM) — or time to position read/write head (non-RAM)	All memory types	Registers: <1 ns · L1 cache: 1–4 ns · DRAM: 50–100 ns · SSD: 50–100 µs · HDD: 5–15 ms
Cycle Time	Access time + recovery time before next access can begin. For DRAM: includes precharge and refresh overhead.	Primarily random-access memory	DRAM cycle time ≈ 2× access time due to destructive read + restore
Transfer Rate	Rate at which data moves in or out. For RAM: 1/Cycle Time. For non-RAM: TN = TA + N/R where N=bits, R=bit rate	All memory types	DDR5-6400: ~51 GB/s · SATA SSD: ~500 MB/s · HDD: ~200 MB/s

Why cycle time > access time for DRAM: DRAM cells store charge on capacitors. A read is destructive — the act of sensing the charge partially drains the capacitor. After every read, the controller must restore the charge. This restoration phase (precharge + restore) adds time after access before the next access can begin. SRAM uses flip-flops (non-destructive read) and has no restore overhead — cycle time ≈ access time.

🔋Physical Types & Volatility

Property	Volatile	Non-Volatile
Definition	Information is lost when power is removed	Information persists without power
Semiconductor examples	SRAM, DRAM	ROM, PROM, EPROM, EEPROM, Flash, FeRAM
Other technology examples	—	Magnetic tape, HDD, optical disc
Typical use	Working memory (programs, data during execution)	Storage (firmware, OS, files, configuration)

Property	Erasable	Non-Erasable
Definition	Contents can be modified after manufacture	Contents are fixed at manufacture — cannot be changed
Examples	SRAM, DRAM, EEPROM, Flash	Mask ROM (traditional)
Implication	Software can be updated, bugs fixed in field	Any change requires replacing the chip

🔲Semiconductor Memory — RAM

Despite the name, RAM (Random Access Memory) is used specifically to mean read-write, volatile semiconductor memory. Two types exist:

SRAM — Static RAM

Each bit stored as a bistable flip-flop (cross-coupled inverters)
Data held as long as power is applied — no refresh needed
Read is non-destructive — flip-flop state unchanged after read
Faster access time (1–10 ns)
Larger cell area — 6 transistors per bit
More expensive per bit
Lower density → used for small, fast cache memories
Digital storage (flip-flop is binary — cleanly 0 or 1)

DRAM — Dynamic RAM

Each bit stored as charge on a capacitor
Capacitor charge leaks → must be refreshed every ~64 ms
Read is destructive — capacitor partially discharged by sensing
Slower access (50–100 ns) and requires refresh overhead
Smaller cell area — 1 transistor + 1 capacitor per bit
Less expensive per bit → much higher density
Used for large main memory (GBs)
Analogue storage (charge level determines 0 or 1)

⚖️SRAM vs DRAM — Side-by-Side

Figure 2 — SRAM cell (6T flip-flop) vs DRAM cell (1T1C capacitor)

SRAM cell (left): 6 transistors forming two cross-coupled inverters. Bistable — holds state indefinitely without refresh. BL and BL̄ are complementary bit lines; Word Line (WL) activates the access transistors for read/write. DRAM cell (right): 1 transistor + 1 capacitor. Charge on the capacitor represents the bit. Leakage requires periodic refresh. Read is destructive — charge must be restored after sensing.

Feature	SRAM	DRAM
Storage element	Flip-flop (cross-coupled inverters)	Capacitor + access transistor
Transistors per bit	6	1 (+ 1 capacitor)
Refresh required?	No	Yes — every ~64 ms
Read destructive?	No	Yes — capacitor partially drained
Access time	1–10 ns (faster)	50–100 ns (slower)
Density	Low (large cell)	High (small cell)
Cost per bit	High	Low
Power	Low (static dissipation)	Higher (refresh + switching)
Primary use	Cache (L1/L2/L3), register files	Main memory (GB-scale)

📖ROM Family — Read-Only Memory Types

ROM (Read-Only Memory) is non-volatile semiconductor memory. The term covers a family of technologies ranging from mask-programmed (at manufacture) to electrically rewritable:

Figure 3 — ROM family: programming method, erase method, and typical use

ROM family tree. All four types are non-volatile. Mask ROM is cheapest for high-volume but cannot be changed. PROM can be programmed once by the user. EPROM can be erased by UV light and reprogrammed. EEPROM/Flash can be erased and reprogrammed electrically, in-system — enabling firmware updates without removing the chip.

Type	Category	Programmed by	Erase method	Volatile?
RAM	Read-write	CPU (byte-level, in-system)	Electrically (byte-level)	Yes
Mask ROM	Read-only	Photolithography masks at fab	Not possible	No
PROM	Read-only after programming	PROM programmer (one time)	Not possible (fuse)	No
EPROM	Read-mostly	PROM programmer, multiple times	UV light (~20 min, whole chip)	No
Flash	Read-mostly	CPU / programmer (block-level)	Electrically (block/sector)	No
EEPROM	Read-mostly	CPU / programmer (byte-level)	Electrically (byte-level)	No

Flash vs EEPROM: Flash erases in blocks (sectors of 4 KB–64 KB) and is much denser and cheaper than EEPROM. EEPROM erases at individual byte level — more flexible but less dense. Modern microcontrollers (STM32, nRF52) use Flash for program storage (hundreds of KB to MBs) and EEPROM emulation in Flash for configuration data.

⚡Advanced DRAM — SDRAM, DDR, Burst Mode

Basic DRAM is asynchronous. Modern systems use Synchronous DRAM (SDRAM), which synchronises all operations to the system clock, enabling predictable timing and burst transfers:

DRAM type	Key advancement	Transfer rate
Basic DRAM	Asynchronous; CPU stalls waiting for data; no burst mode	~100 MB/s
SDRAM	Synchronised to system clock; CPU knows when data arrives; burst mode	~800 MB/s (PC100)
DDR SDRAM	Double Data Rate — transfers on both rising and falling clock edges	~1.6 GB/s (DDR-200)
DDR4	Lower voltage (1.2V), higher density, higher frequency	~17–25 GB/s
DDR5	64-bit channel split into two 32-bit sub-channels; on-die ECC; 1.1V	~25–51 GB/s

Burst mode: Once an initial address is presented, SDRAM can automatically increment the address and output consecutive words without new address cycles. A cache line fill (64 bytes = 8 × 64-bit words) with burst mode requires 1 address cycle + 8 data cycles = 9 cycles vs 16 cycles without burst — a 44% reduction.

🏔️Memory Hierarchy & Cache

No single memory technology satisfies all requirements simultaneously. The solution is a memory hierarchy — multiple levels of storage, each faster but smaller and more expensive than the level below:

Figure 4 — Memory hierarchy pyramid: speed, cost, and capacity

Memory hierarchy pyramid. Speed decreases and capacity increases from top to bottom. The cache hierarchy bridges the gap — SRAM caches hold recently used data, so most accesses hit cache (fast) rather than going to DRAM (slow). A typical L1 cache hit rate is 90–99%.

Why cache works — locality of reference

Temporal locality: A memory location accessed recently is likely to be accessed again soon. (Loops execute the same instructions repeatedly.)
Spatial locality: If a memory location is accessed, nearby locations are likely to be accessed soon. (Array iteration accesses consecutive addresses.)

Cache line fetches exploit spatial locality by fetching 64 bytes at once even though only 4 bytes were requested — the adjacent bytes will likely be needed next.

🛡️Error Detection & Correction

Memory errors occur in two forms:

Hard failure: Permanent physical defect in a memory cell — always reads the wrong value. Must be replaced.
Soft error: Random, transient bit flip caused by cosmic radiation (alpha particles, neutrons). No permanent damage — ECC is designed to detect and correct these.

Hamming Error Correcting Code (ECC): Adds redundant check bits alongside data bits. For 8-bit data, 4 check bits allow: (1) detection of all 1-bit and 2-bit errors, (2) correction of any single-bit error. Modern DDR5 adds 8 ECC bits per 64-bit data word. ECC RAM is mandatory in servers, workstations, and safety-critical embedded systems.

🔍 Worked Example — Hamming distance and error detection

Principle: Hamming distance = number of bit positions where two codewords differ. To detect d errors, need Hamming distance ≥ d+1. To correct d errors, need distance ≥ 2d+1.

For SECDED (Single-Error Correction, Double-Error Detection): Need Hamming distance = 4. For 64 data bits, SECDED requires 8 check bits (72 bits total stored). DDR5 uses this exact scheme.

Check bit positions: Check bits occupy positions that are powers of 2 (1, 2, 4, 8, 16, 32, 64…). On a mismatch, the syndrome (XOR of failing check bits) gives the exact position of the erroneous bit, enabling correction.

🔬VLSI Connections

🔬 SRAM macros — the most common cell in every SoC

Every SoC contains dozens to hundreds of SRAM macros — register files, L1 instruction and data caches, L2 caches, shared L3 cache, TLB arrays, FIFO buffers, scratchpad memories. SRAM macros are generated by memory compilers (ARM SRAM Compiler, Faraday Memory, TSMC SRAM) that take capacity, word width, and read/write ports as inputs and produce verified GDS2, LEF, timing characterisation (.lib), and simulation models. During physical design, SRAM macros are hard IP blocks — their internal layout is fixed, and your job is to place them, manage power straps, and close timing on their input/output ports.

🔬 Flash in SoC — NOR Flash for code, NAND Flash for data

Embedded microcontrollers (ARM Cortex-M series) integrate NOR Flash directly on-die for program storage. NOR Flash allows random-access reads at byte granularity — the CPU can execute code directly from NOR Flash (XIP — execute-in-place) without copying to RAM first. NAND Flash (the technology in SSDs and USB drives) only supports page-level random access reads and must be copied to RAM before execution, but achieves 10–100× higher density than NOR. When you do SoC integration on a Cortex-M design, you will connect the embedded NOR Flash macro to the instruction bus and the DRAM or SRAM to the data bus — a modified Harvard architecture in hardware.

🔬 ECC in VLSI — mandatory for safety-critical and server silicon

Every SRAM macro in a safety-critical SoC (automotive ASIL-D, avionics DO-254 Level A) must have ECC. The synthesised ECC logic (Hamming encoder on write, decoder + corrector on read) adds area — typically 12.5% overhead (8 ECC bits per 64 data bits). Automotive SoC designs for ASIL-D go further: SRAM is either implemented with ECC or with lockstep redundancy (two copies of the compute hardware running in parallel, outputs compared every cycle). ISO 26262 mandates ECC or lockstep for safety integrity.

Summary — CA-06 key points: Memory systems are characterised by location, capacity, unit of transfer, access method, performance, physical type, and volatility. Four access methods: sequential (tape), direct (disk), random (DRAM/SRAM — constant time), associative (CAM — parallel content search). Three performance parameters: access time, cycle time (≥ access time for DRAM), transfer rate. SRAM (6T flip-flop, fast, non-destructive, no refresh, expensive) is used for cache. DRAM (1T1C capacitor, slow, destructive read, needs refresh, cheap) is used for main memory. ROM family: Mask ROM (manufacture), PROM (one-time user), EPROM (UV erase), EEPROM (byte-level electrical erase), Flash (block-level electrical erase). Memory hierarchy exploits locality of reference. ECC detects and corrects single-bit errors using Hamming codes — mandatory in servers and safety-critical systems.