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Who this series is for. Engineers and students who want to understand how computers work at the hardware level — not just software. Each article connects CPU design, memory hierarchy, and I/O architecture directly to the VLSI concepts you need for chip design interviews and verification roles. Articles follow the DE series format: concept → block diagram → worked example → VLSI connection.
Prerequisites: Digital Electronics series (DE-01 through DE-12) recommended — especially Boolean logic (DE-03/04), combinational circuits (DE-05/06), flip-flops (DE-08), and memories (DE-12). Number systems (DE-01) and binary arithmetic (DE-02) are assumed throughout.
CA-01
What a computer is, how it accepts, stores, processes, and returns information. A timeline from abacus to ENIAC to transistors to ICs. Mark I, ENIAC’s 17,000 vacuum tubes, and the pivotal role of the transistor. How each hardware era maps to modern chip design.
Concept
Architecture
VLSI Link
CA-02
Five generations of computers: vacuum tubes, transistors, ICs, microprocessors, AI/VLSI era. Classification by size and capability: supercomputers, mainframes, minicomputers, workstations, PCs, embedded systems. How technology scaling maps to Moore’s Law and modern SoC design.
Concept
Architecture
VLSI Link
CA-03
Von Neumann model: stored-program concept, single shared memory for data and instructions. Four key structural components: CPU, main memory, I/O, and the system bus. Top-down functional analysis. Harvard vs Von Neumann. How modern SoCs extend this classical model with caches and memory hierarchies.
Architecture
Diagram
VLSI Link
CA-04
What a bus is and why it matters. Bus structure: address, data, and control lines. Five elements of bus design: type (dedicated vs multiplexed), arbitration (centralised vs distributed), timing (synchronous vs asynchronous), bus width, and data transfer types. Worked timing diagrams for synchronous and asynchronous buses.
Architecture
Diagram
VLSI Link
CA-05
The basic instruction cycle: fetch, decode, execute. Instruction cycle state diagram — with and without interrupts. What an interrupt is, why it exists, and how it improves CPU utilisation. Interrupt service routines, return addresses, and nested interrupts. Multiple interrupt classes and priority schemes. Timing diagrams for interrupt-driven execution.
Architecture
Diagram
Concept
VLSI Link
CA-06
Key characteristics of memory systems: location, capacity, unit of transfer, access method (sequential, direct, random, associative), performance (access time, cycle time, bandwidth), and physical type. SRAM vs DRAM. ROM family: mask ROM, PROM, EPROM, EEPROM, Flash memory. Cache organisation and hit/miss concepts. Memory hierarchy pyramid.
Hardware
Diagram
VLSI Link
CA-07
Cache design: direct-mapped, fully associative, and set-associative mapping. Cache replacement policies: LRU, FIFO, random. Write-through vs write-back. Virtual memory concept: address spaces, page tables, TLB. Memory management unit (MMU). How caches and virtual memory interact in modern SoC designs.
Hardware
Architecture
VLSI Link
CA-08
I/O in the computer system: why a dedicated I/O module is needed. External devices: keyboard, monitor, disk, network. I/O module functions: control and timing, CPU communication, device communication, data buffering, error detection. The I/O module as a miniature processor. Status, control, and data registers.
I/O
Architecture
Diagram
CA-09
Three I/O techniques compared: (1) Programmed I/O — CPU polls, simple but wastes cycles. (2) Interrupt-driven I/O — CPU interrupted when device is ready, ISR handles transfer. (3) DMA — direct memory access, DMA controller transfers blocks without CPU intervention. Timing diagrams for all three. DMA cycle-stealing vs burst mode.
I/O
Diagram
VLSI Link
CA-10
CPU internals: register file, ALU, control unit. Register types: general-purpose, program counter, instruction register, stack pointer, status/flags. ALU operations: integer arithmetic, logical, shift/rotate. RTL (Register Transfer Language) representation. How a CPU instruction maps to ALU operations at the gate level. RISC vs CISC register architectures.
Hardware
Architecture
Diagram
VLSI Link
CA-11
Binary integer arithmetic: addition, subtraction via 2’s complement, overflow detection. Unsigned and signed multiplication: partial products, Booth’s algorithm introduction. Floating-point representation: sign, exponent, mantissa. IEEE 754 single and double precision. Floating-point addition step-by-step. NaN, infinity, and denormalised numbers.
Concept
Hardware
VLSI Link
CA-12
Basic logic gates: AND, OR, NOT, NAND, NOR, XOR with truth tables. Half-adder and full-adder: sum and carry logic. Half-subtractor and full-subtractor: difference and borrow. 4-bit ripple-carry adder circuit. Sequential logic: SR, D, JK, T flip-flops. How combinational and sequential blocks combine into the ALU and register file in a real CPU RTL design.
Logic
Hardware
Diagram
VLSI Link
🔬 How this series connects to VLSI chip design
Every article links theory to silicon. The Von Neumann architecture (CA-03) is the conceptual model behind every ARM, RISC-V, and x86 core you will verify or integrate. Bus design (CA-04) maps directly to AXI, APB, and AHB interconnects inside every SoC. Interrupts (CA-05) are the architectural basis for interrupt controllers (GIC in ARM) and edge-sensitive signal handling in RTL. The memory hierarchy (CA-06/CA-07) determines the microarchitecture of your L1/L2/L3 cache blocks. DMA (CA-09) is the architecture behind the AMBA DMA-330 controller. The ALU and combinational logic (CA-10/CA-12) is the gate-level content you synthesise every day. Each VLSI connection callout (purple box) in every article makes this link explicit.
