Connecting multiple slaves to one SPI master — the two topologies, their trade-offs, how tristate buffers solve the MISO conflict, and how daisy-chaining turns a bus into a giant shift register.
A standard SPI channel connects one master to one slave. But in real embedded systems — a PCB with an accelerometer, a DAC, a flash chip, and a display controller — all sharing one SPI bus off a single microcontroller — you need to connect multiple slaves to one master.
This creates two specific problems that the basic SPI channel design does not address:
The basic SPI channel has one SS wire. Asserting it LOW selects the slave. With multiple slaves, asserting this single wire would activate all slaves simultaneously — every slave would try to respond to the exchange at the same time.
If multiple slaves share the same MISO wire and all drive it simultaneously, their outputs conflict. One driving HIGH and another driving LOW creates a short circuit — same as wiring two totem-pole outputs together (from DE-07 logic families).
There are exactly two topological solutions, each solving these problems in a different way:
The independent (parallel) configuration is the more common of the two. Each slave gets its own dedicated Slave Select line from the master. All slaves share the same SCLK and MOSI wires. MISO lines from all slaves are connected together (shorted) — but each slave drives MISO through a tristate buffer.
Independent (parallel) configuration. SCLK and MOSI are broadcast to all slaves via shared vertical rails. Each slave has its own dedicated SS̄ line entering its top pin. All slave MISO outputs connect to a shared vertical MISO rail (right side), each through a tristate buffer (⊗) — only the selected slave drives the bus; the rest are in Hi-Z.
The tristate buffer (three-state buffer) is what makes the shared MISO wire safe. It has three possible output states:
| Enable (SS̄) | Input | Output |
|---|---|---|
| 0 (selected) | data bit | drives 0 or 1 normally |
| 1 (not selected) | any | Hi-Z (high impedance — disconnected) |
When SS̄=LOW (selected), the tristate buffer actively drives its data onto the shared MISO bus. When SS̄=HIGH (not selected), the buffer enters Hi-Z state — its output is electrically disconnected from the MISO bus, as if the wire was cut. Only one slave is selected at a time, so only one buffer drives MISO.
From a timing perspective, independent configuration looks identical to a single-slave exchange. The only difference is which SS̄ line is asserted. All three slaves see SCLK and MOSI, but only the selected slave responds on MISO.
Only SS2̄ is asserted LOW. SS1̄ and SS3̄ remain HIGH — Slaves 1 and 3 are idle with their MISO tristate buffers in Hi-Z. Slave 2 drives the shared MISO bus. SCLK and MOSI reach all three slaves, but only Slave 2 processes them.
The daisy-chain configuration takes a completely different approach. Instead of individual SS lines, there is a single shared SS wire. Instead of separate MISO lines, the MISO of each slave connects to the MOSI of the next slave — forming a single long shift-register chain through all slaves back to the master.
Daisy-chain configuration. SCLK and SS̄ are broadcast to all slaves. Master’s MOSI drives Slave 1’s MOSI. Slave 1’s MISO drives Slave 2’s MOSI. Slave 2’s MISO drives Slave 3’s MOSI. Slave 3’s MISO returns to the master. This forms a single long shift register: Master→S1→S2→S3→Master.
With 3 slaves, one exchange in daisy-chain mode is 3 × 8 = 24 bits long (SS̄ stays LOW for 24 clock cycles). Here is exactly what happens at each stage:
Daisy-chain bit flow for 3 slaves. Master sends B2 first (for Slave 3), then B1 (for Slave 2), then B0 (for Slave 1). After 24 clock cycles, each slave’s shift register contains exactly one byte. When SS̄ deasserts, all slaves simultaneously capture their byte.
With s slaves in daisy-chain, every exchange uses s × 8 clock cycles. All slaves participate in every exchange — there is no way to address just one slave. This is the fundamental constraint of daisy-chain topology.
| Number of slaves (s) | Exchange length (bits) | Clock cycles per exchange | Bytes transmitted |
|---|---|---|---|
| 1 | 8 | 8 | 1 |
| 2 | 16 | 16 | 2 |
| 3 | 24 | 24 | 3 |
| 4 | 32 | 32 | 4 |
| s | s × 8 | s × 8 | s |
Setup: 1 master + 3 slaves in daisy-chain, CPOL=0, CPHA=0, MSB first. Master needs to send: 0x42 to Slave 1, 0x17 to Slave 2, 0xF0 to Slave 3.
Transmission order (last slave first):
Cycles 1–8: 0xF0 (for Slave 3)
Cycles 9–16: 0x17 (for Slave 2)
Cycles 17–24: 0x42 (for Slave 1)
After 24 cycles, SS̄ deasserts. Each slave latches what is in its shift register:
Slave 1 shift reg = 0x42 ✓
Slave 2 shift reg = 0x17 ✓
Slave 3 shift reg = 0xF0 ✓
Why? 0xF0 was sent first and travelled through S1 (8 cycles) then S2 (8 cycles) to reach S3’s shift register by cycle 24. 0x42 was sent last and is still in S1’s shift register when SS̄ deasserts.
| Feature | Independent | Daisy-Chain |
|---|---|---|
| SS lines required | 1 per slave (N total) | 1 shared |
| MOSI wires | 1 shared | 1 between each pair (same net) |
| MISO wires | 1 shared (tristate) | separate per slave (chained) |
| Tristate buffers needed? | Yes — on each slave MISO | No — each MISO drives only the next MOSI |
| Exchange length | 8 bits | s × 8 bits |
| Address one slave selectively? | Yes — assert only that SS̄ | No — all slaves participate |
| Byte transmission order | Normal | Reversed (last slave first) |
| Max slaves limited by… | Available GPIO pins for SS̄ | Exchange timing budget (latency ∝ s) |
| Typical use cases | Mixed peripheral buses (ADC + DAC + flash) | LED shift registers, scan chain testing, identical device arrays |
The tristate buffer on MISO in independent configuration is a direct application of the open-collector / tristate output concepts from DE-07 (Logic Families). The same circuit technique is used for the I²C bus (open-drain + pull-up), the CPU data bus (tristate drivers on each source), and DDR memory data buses (on-die termination with controlled impedance). The concept is identical: multiple potential drivers share one wire, but only one drives at a time — enforced either by explicit enable signals (tristate) or by pull-up and open-drain design (wired-AND). Bus contention, when two drivers fight, causes exactly the current-spike problem discussed in DE-07 totem-pole conflict.
JTAG (IEEE 1149.1), the standard test access port used in every modern chip, is architecturally identical to SPI daisy-chain. TDI (Test Data In) is MOSI, TDO (Test Data Out) is MISO, TCK is SCLK, TMS is SS. When multiple JTAG devices are on a board, they are connected in a daisy-chain with TDO→TDI between each device — exactly Figure 4. The shift register inside each JTAG device is the device’s scan chain. Understanding SPI daisy-chain gives you the mental model for how DFT scan chains and JTAG work at the board level.
On a typical SoC PCB, the MCU or application processor has a fixed number of GPIO pins available for SPI SS̄. A high-density design might use a 3-to-8 decoder IC on three GPIO outputs to drive up to 8 SS̄ lines — exactly the decoder design from DE-06 (Combinational Circuits). This trades 3 GPIO pins for 8 device-select signals. Alternatively, an I/O expander IC (itself connected over SPI in independent config!) adds more GPIO pins. The hardware-level decision between independent and daisy-chain topology is made during PCB design and RTL SoC integration — both require the engineer to understand what is happening at the wire level.