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Who this series is for. VLSI design, embedded systems, and verification engineers who need to understand how SPI works at the wire level — including timing modes, transaction decoding, and how SPI maps to programmed I/O. Each article includes interactive WaveDrom timing diagrams built directly from the protocol specification. Articles follow the DE series format: concept → worked example → VLSI connection.
Prerequisites: Digital Electronics series (DE-01 through DE-08) — especially flip-flops (DE-08), shift registers (DE-09), and synchronous/asynchronous concepts from logic families (DE-07). Familiarity with binary and hex conversion (DE-01) assumed throughout.
SPI-01
What a communication protocol is, how synchronous differs from asynchronous (UART, PLL clock recovery), and an introduction to SPI’s four wires: SCLK, SS, MOSI, MISO. Master-slave architecture explained.
Concept
Protocol
VLSI Link
SPI-02
Deep dive into CPOL and CPHA — how they define clock polarity and phase, the four timing mode combinations (Mode 0/1/2/3), aperture time, metastability risk, and bit ordering (MSB-first vs LSB-first).
Timing
Concept
SPI-03
How a single 8-bit SPI exchange works across all four CPOL/CPHA modes. Reading and drawing timing diagrams. Worked decoding exercise (CPOL=1, CPHA=1, MSB-first → 0xB5).
Timing
Protocol
SPI-04
How multiple exchanges combine into read and write transactions. Header format (address + R/W + stream flags). Unused wire behaviour. Burst/streaming multi-byte transactions with length encoding.
Protocol
Concept
VLSI Link
SPI-05
Connecting multiple slaves to one master. Independent configuration (dedicated SS per slave, shared MISO with tristate buffers). Daisy-chain configuration (single SS, shift-register data path, s×8 exchange length).
Concept
VLSI Link
SPI-06
Reading VCD-style signal trace files. Implementing a protocol decoder in software (Python/C). Decoding single exchanges, streaming transactions, and flexible CPOL/CPHA modes. Full graded lab project.
Timing
Lab
VLSI Link
🔬 VLSI Connections throughout this series: SPI is used everywhere in chip design — SoC boot-ROM configuration over SPI, ADC/DAC sensor interfaces, EEPROM programming, FPGA configuration (JTAG is SPI-derived), and PCIe sideband management. DFT scan chains are structurally identical to SIPO/PISO shift registers, and SPI decoding is the foundation for protocol-aware testbench writing in SystemVerilog.