All 11 LTSSM states with every substate — what happens in each, how the transitions work, the full Detect→Polling→Configuration→L0 power-on walkthrough, Recovery substates, power states L0s/L1/L2, Hot Reset, Disabled, Loopback, and Gen 6 additions.
The Link Training and Status State Machine (LTSSM) is the hardware state machine inside every PCIe Physical Layer that manages the link from power-on to full operation. It runs entirely in hardware — no software involvement during link training. Software only observes the outcome through Link Status register bits and can initiate certain transitions (like Retrain Link or Enter Compliance) via Link Control registers.
The LTSSM has 11 primary states, each with between 1 and 5 substates. When two PCIe devices are connected and power is applied, both LTSSMs start at Detect independently and work through the state machine simultaneously until both reach L0 — the fully operational state where TLPs and DLLPs flow normally.
Link training is not just about making a connection — it negotiates and configures six distinct link properties before the first TLP can flow:
| Property | What is negotiated | State where resolved |
|---|---|---|
| Bit Lock | Receiver CDR locks onto transmitter clock from the incoming bitstream. Must happen before any symbol or block interpretation is possible. | Polling.Active |
| Symbol/Block Lock | For 8b/10b: find 10-bit symbol boundaries using COM character. For 128b/130b (Gen 3+): find 130-bit block boundaries using sync header pattern via EIEOS. | Polling.Active |
| Link Width | Both devices advertise how many lanes they have. The highest common width is selected. A x4 device connecting to a x16 slot trains to x4. | Configuration.Linkwidth.Start/Accept |
| Lane Numbers | Each lane gets a logical number (0 to N-1). Lane reversal may be applied if PCB routing requires it (supported by at least one end). | Configuration.Lanenum.Wait/Accept |
| Polarity Inversion | If D+ and D− are swapped on a lane (common PCB layout shortcut), the receiver detects and internally corrects it. Mandatory support. | Polling.Configuration |
| Data Rate | Always starts at 2.5 GT/s for backward compatibility. Higher rates are advertised in TS1/TS2 Rate ID field. Actual rate change happens in Recovery after initial L0 is reached. | Recovery.Speed (first L0 entry) |
| Equalization (Gen 3+) | Tx FIR coefficients are negotiated. Receiver requests specific preset values. Multiple equalization phases may run. | Recovery.Equalization |
| Lane Deskew | On wide links, different lanes arrive at slightly different times. Receiver delays early arrivals to align all lanes before packet reassembly. | Configuration.Complete |
| N_FTS | Number of Fast Training Sequences needed to exit L0s. Receiver tells transmitter how many FTS ordered sets to send when waking the link from L0s standby. | Configuration.Complete (from TS2) |
TS1 and TS2 (Training Sequences) are the primary ordered sets used during link training. They are 16 symbols long and carry all the training parameters. TS1 means “I am training but not yet done.” TS2 means “I am ready to move to the next state — are you?” When both sides are sending TS2, they can advance together.
Entry point after any reset. The transmitter has never driven the link before and does not know whether a receiver is connected. Everything starts at 2.5 GT/s and the link is in electrical idle.
First state after power-on or cold reset. Entered within 20 ms of reset deassertion.
Exit to Detect.Active: after 12 ms timeout, or immediately if any lane exits electrical idle.
The transmitter actively probes for a receiver on each lane. It sets a DC common-mode voltage on the lane, then quickly changes it and measures how fast the voltage transitions.
Exit to Polling: one or more lanes detect a receiver (even after the 12 ms patience window).
Exit back to Detect.Quiet: no lanes detect a receiver after the 12 ms probe. Loop repeats every 12 ms.
The link exits electrical idle. TS1 and TS2 ordered sets are exchanged. Both devices acquire Bit Lock (CDR locks onto transmitter clock) and either Symbol Lock (8b/10b) or Block Alignment (128b/130b). Polarity inversion is detected and corrected.
Transmitters drive the link out of electrical idle and begin sending TS1 ordered sets on all detected lanes simultaneously.
Exit to Polling.Configuration: after sending ≥1024 TS1s, ALL detected lanes receive 8 consecutive TS1s or TS2s with PAD lane/link numbers AND Compliance Receive bit = 0. Or after a 24 ms timeout if ANY lane met this condition and all lanes had an electrical idle exit.
Exit to Polling.Compliance: Enter Compliance bit set in Link Control 2, or timeout with compliance conditions detected on any lane.
Exit to Detect: 24 ms timeout with insufficient response.
Handshake phase. Having achieved lock, the transmitter switches from TS1 to TS2 to signal “I am ready to proceed to Configuration.” The link partner switches to TS2 when it is also ready. When both sides are sending and receiving TS2, both can advance.
Exit to Configuration: after receiving 8 consecutive TS2s (with PAD link/lane, Compliance Receive=0) on any detected lane AND sending at least 16 TS2s after receiving one.
Exit to Detect: 48 ms timeout without satisfying the TS2 handshake.
A special testing state used exclusively for hardware characterisation. Reached when the Enter Compliance bit is set in Link Control 2, or when a compliance pattern is requested via incoming TS1 Compliance Receive bits.
Exit to Polling.Active: Enter Compliance bit cleared, or EIOS detected (if upstream port).
Link width and lane numbers are negotiated. TS1 and TS2 ordered sets now carry real link and lane numbers (not PAD). The six substates implement a negotiation→confirmation→idle sequence that concludes with LinkUp assertion and the link entering L0.
The Downstream Port initiates link width negotiation by sending TS1s with a unique Link Number on each lane and PAD in the Lane Number field.
Exit to Linkwidth.Accept: a single Link Number is confirmed for a set of lanes (the downstream port has learned the width).
The Upstream Port responds to the Downstream Port’s proposed Link Numbers in TS1s. It echoes back the same Link Number on all lanes that belong to the same link, signalling which lanes will be grouped together.
Lane numbers (within the chosen link width) are assigned. Downstream Port sends TS1s with the agreed Link Number and assigns Lane Numbers 0 through N-1 sequentially. Upstream Port sends TS1s echoing the same Link Number with PAD in Lane Number.
Both ports have received matching Lane Numbers from each other. Both now echo back TS1s with matching Link and Lane numbers — confirming the assignment. Lane-to-lane deskew is performed during this substate: the receiver delays early-arriving lanes to align with the slowest lane, compensating for trace length differences on the PCB.
The switch from TS1 to TS2. Once a device has matched Link and Lane numbers, it starts sending TS2 to signal “I am done with configuration and ready for L0.” This is the same TS1→TS2 handshake as in Polling, but now with real link and lane numbers.
Exit to Configuration.Idle: all configured lanes received 8 consecutive TS2s with matching Link and Lane numbers AND rate identifiers, after sending at least 16 TS2s.
Exit to Detect: 2 ms timeout without successful TS2 handshake completion.
The final configuration substate. Transmitters stop sending TS2 and switch to sending Idle data (all-zero bytes that get scrambled). This is the bridge between configuration and L0.
Exit to L0: 8 consecutive Idle data symbols received on all configured lanes, after sending 16 Idle symbols since receiving one.
Exit to Recovery: 2 ms timeout (equalization problem or speed issue — Recovery.RcvrLock retries). Limited to 256 attempts (idle_to_rlock_transitioned counter).
Exit to Detect: if 256 Recovery attempts have failed (counter overflows to FFh).
L0 is the only state where TLPs and DLLPs are exchanged. The Physical Layer has set LinkUp=1, Flow Control has completed initialisation, and the link is ready for normal traffic. This is the state that software observes as the “link is up.”
Note: the LTSSM for the transmitter side and receiver side of a port can be in different states simultaneously in L0. One direction can be in L0s while the other remains in L0 — this is the fundamental property that enables ASPM L0s.
Recovery is the maintenance state. Either device can initiate it from L0 by starting to send TS1 ordered sets on configured lanes. When the partner sees incoming TS1s, it also enters Recovery and returns TS1s. Both devices then re-acquire Bit Lock and Symbol/Block Lock, and perform whatever specific task caused Recovery to be entered.
Recovery is how link speed is changed after initial L0 (always from 2.5 GT/s to the highest mutually supported speed). Recovery is also how equalization is redone, how link width is changed, and how an AER-triggered link retrain is handled.
Both ports send TS1 ordered sets on all configured lanes using the Link and Lane numbers that were set in Configuration. The receiver re-acquires Bit Lock and Symbol/Block Lock from these TS1s.
Exit to Recovery.RcvrCfg: 8 consecutive TS1s or TS2s received with matching Link/Lane numbers and speed_change bit matching directed_speed_change, AND EC field = 00b (no equalization request).
Exit to Recovery.Equalization: at 8 GT/s, if the incoming TS1s request equalization (EC field non-zero), or if equalization conditions require it.
Exit to Recovery.Speed: conditions indicate the current speed cannot be maintained — fall back to a lower speed.
Exit to Configuration: if no speed change was requested (speed_change=0 in TS1s), go to Configuration to renegotiate link width.
Exit to Detect: 24 ms timeout with no recovery conditions met.
Three-phase equalization process for Gen 3 links. The receiver evaluates the signal quality with different Tx FIR coefficient settings and converges on the optimal values. This substate only runs when changing to or operating at 8 GT/s and one or more equalization phases need to be executed.
Lock re-acquired. Speed agreed. Equalization done (if needed). Now the devices switch from TS1 to TS2 — the familiar “I am done, are you ready?” handshake used in Polling.Configuration and Configuration.Complete.
Exit to Recovery.Speed: if a speed change was agreed (speed_change=1 in TS1s and TS2s).
Exit to Recovery.Idle: if no speed change — just re-locking from an error or returning from L1/L0s. Received 8 TS2s, sent 16 TS2s.
Exit to Configuration: if width change needed — link width renegotiation requires going through Configuration again.
Exit to Detect: 48 ms timeout.
The actual speed transition. All lanes briefly enter electrical idle, the clock rate is changed and stabilised, and then the link comes back up at the new speed.
Transitioning back to L0. Same purpose as Configuration.Idle — sending Idle data while confirming the link is stable before asserting it operational.
Exit to L0: 8 consecutive Idle symbols received, 16 sent. idle_to_rlock_transitioned counter cleared.
Exit to Hot Reset: if TS1s with Hot Reset bit set received.
Exit to Disabled: if directed to disable.
Exit to Detect: if recovery has failed enough times.
L0s is a hardware-initiated low-power state for individual link directions. Unlike L1 which requires both directions to be low-power, L0s is asymmetric — one direction can be idle (in L0s) while the other continues normal operation. This is useful for bursty traffic where one direction is much lighter.
Entry/exit is entirely hardware-controlled (ASPM — Active State Power Management). No software or DLL involvement. Exit latency is very short — typically a few hundred nanoseconds.
Transmitter initiates L0s entry. It sends EIOS (Electrical Idle Ordered Set) on all lanes and then stops driving the differential pair, entering electrical idle. The far-end receiver detects EIOS, transitions to L0s receive mode, and stops expecting transmissions.
Transmitter is in electrical idle. The PLL may stay running at reduced power. The transmitter saves energy by not driving the high-frequency differential signal. Entry into this state may be held for as long as no packets are waiting to send.
When the transmitter has TLPs or DLLPs to send, it exits L0s by sending FTS (Fast Training Sequences) ordered sets. The number of FTS ordered sets sent equals the N_FTS value that was negotiated during Configuration.Complete — the far-end receiver told the transmitter exactly how many it needs to re-achieve lock.
L1 is a deeper power state than L0s where both transmitter and receiver in both link directions enter electrical idle simultaneously. Both devices must agree to enter L1 via a DLL-level handshake before either can initiate. PLLs may be turned off, saving significantly more power than L0s — but exit latency is longer, typically a few microseconds.
After the DLL handshake confirms both sides are ready, the initiating device sends EIOS on all lanes (one EIOS at 2.5 GT/s, two at 5.0 GT/s). Both transceivers then enter electrical idle. The PLL is allowed to power down.
Both directions idle. Device logic continues running but at reduced power. Exit is initiated by hardware detecting that packets need to flow, or by software request. Exit from L1 goes through Recovery — there is no fast exit path like FTS in L0s. Recovery re-establishes lock and brings the link back to L0.
L2 is the deepest link power state. Main power to the device is removed. Only Vaux (auxiliary voltage, typically 3.3V standby) keeps a minimal wake circuit operational. The transmitter and receiver are completely off.
Device is in main power-off state. Vaux keeps the wake detector and Beacon generation logic alive. Device cannot receive TLPs or DLLPs.
Two wake mechanisms exist. The Beacon is a low-frequency differential signal that a device can drive onto the link from Vaux power to signal the Root Complex that it wants to wake. The WAKE# sideband pin is an alternative — a direct signal from device to Root Complex that does not require the link pair itself. When a wake event is detected, power is restored and the LTSSM eventually transitions back to Detect and performs a full link re-training sequence.
Hot Reset is an in-band reset mechanism where an upstream device resets a downstream device without removing power. It is signalled by setting the Hot Reset bit in TS1 ordered sets sent during Recovery.Idle or from L0. When the downstream device receives TS1s with Hot Reset = 1, it asserts its own internal reset and also propagates Hot Reset downstream through its ports.
The Disabled state is entered when software sets the Link Disable bit in the Link Control register, or when the LTSSM receives TS1s with the Disable Link bit set from the link partner. It is also used when a link encounters persistent reliability problems that equalization cannot solve.
Disabled is a clean administrative mechanism — no TLPs are lost because the DLL had already drained before the physical layer disabled the link.
Loopback is a factory/field test mode where one device (the Master) drives patterns onto the link and the other device (the Slave) receives them and immediately retransmits them back. The Master can verify link quality by comparing what it sent with what comes back. Loopback operates at the Physical Layer — TLPs are not processed.
This is the exact sequence a pair of PCIe devices follows from power-on to the first TLP flowing. The sequence runs in parallel on both devices simultaneously.
The first L0 is always at 2.5 GT/s. If both devices support higher speeds and have advertised them in their Rate ID fields during training, one device immediately sets directed_speed_change = 1 and enters Recovery.RcvrLock. The link changes speed to the highest commonly supported rate — Gen 2 (5 GT/s), Gen 3 (8 GT/s), Gen 4 (16 GT/s), or Gen 5 (32 GT/s) — through Recovery.Speed. For Gen 3+ links, Recovery.Equalization runs to negotiate Tx FIR coefficients. The entire speed change from first L0 to operating speed takes roughly 1–5 ms depending on equalization complexity.
The LTSSM structure — 11 states, all substates, the Detect/Polling/Configuration/Recovery sequence — is carried forward unchanged into Gen 6. What changes is the physical layer technology that runs underneath the LTSSM and some Gen 6-specific additions in Training Sequences.
| LTSSM feature | Change in Gen 6 |
|---|---|
| State structure | Unchanged — same 11 states, same substate names, same transition logic |
| TS1/TS2 ordered sets | New Rate ID field encoding for 64 GT/s (PAM4 rate bit). Gen 6 also carries FEC capability negotiation bits in the TS2 equalization fields. |
| Speed change via Recovery | Same Recovery.RcvrLock → Recovery.Speed sequence. 64 GT/s option added to the speed negotiation. |
| Equalization (Recovery.Equalization) | PAM4-specific equalization is far more complex — more equalization phases, multi-tap DFE coefficients, PAM4 eye monitoring. The state machine is the same; the content of the coefficient exchange changes. |
| Flit mode entry | Gen 6 flit mode is negotiated in the TS2 Training Control or in a post-L0 configuration write. The LTSSM itself does not have a flit-specific state — flit framing is transparent to state machine logic above the Physical Layer. |
| Block alignment (128b/130b path) | Gen 6 still starts training at 2.5 GT/s (Gen 1 NRZ) so the initial Polling and Configuration states still use 8b/10b symbol lock. Block alignment (128b/130b) runs when speed changes to Gen 3/4/5 en route to Gen 6. The final transition to 64 GT/s PAM4 goes through Recovery.Speed with PAM4 equalization. |
| FEC capability | RS(544,514) FEC is mandatory for Gen 6. The FEC enable bit is negotiated during the speed change to 64 GT/s, carried in TS2 ordered sets before entering Recovery.Speed. |
| L0s/L1/L2 | Unchanged. Power states work the same at 64 GT/s PAM4 as at lower speeds. EIOS and EIEOS ordered sets still signal entry and exit. |
| State | Substates | Purpose | Key exit condition |
|---|---|---|---|
| Detect | Quiet · Active | Find a receiver on each lane via impedance probing | Receiver detected on at least one lane → Polling |
| Polling | Active · Configuration · Compliance | Acquire Bit Lock + Symbol/Block Lock. Polarity correction. Handshake readiness. | 8 TS2s + 16 sent (after Polling.Config) → Configuration |
| Configuration | Linkwidth.Start · Linkwidth.Accept · Lanenum.Wait · Lanenum.Accept · Complete · Idle | Negotiate link width and lane numbers. Record N_FTS. Assert LinkUp. | 8 Idle symbols received after Configuration.Idle → L0 |
| L0 | (single state) | Normal operation — TLPs, DLLPs, FC, ACK/NAK all running | Speed change request / TS1 received / replay timeout → Recovery |
| Recovery | RcvrLock · Equalization · RcvrCfg · Speed · Idle | Re-lock after error, change link speed, redo equalization, change width | 8 Idle symbols after Recovery.Idle → L0 (at new speed) |
| L0s | Tx_L0s.Entry · Idle · FTS | Per-direction ASPM standby. Transmitter idles, receiver stays active. Fast exit via FTS. | FTS count sent → L0. Lock timeout → Recovery. |
| L1 | Entry · Idle | Both-direction low power. PLLs may power off. Requires DLL handshake to enter. | Traffic needed → Recovery → L0 |
| L2 | Idle · Wake | Main power off. Vaux only. Wake via Beacon or WAKE# pin. | Wake detected → power-on sequence → Detect → L0 |
| Hot Reset | (substates per port) | In-band reset. TS1 with Hot Reset bit = 1. Propagates downstream through switches. | Reset completes → Detect |
| Disabled | (simple) | Link administratively off. High-impedance receiver. Software-controlled. | Link Disable bit cleared → Detect |
| Loopback | Entry · Active · Exit | Physical layer test. Master drives patterns; Slave reflects them. BER measurement. | EIOS from Master → Detect |
| Key timer | Value | Context |
|---|---|---|
| Detect.Quiet → Detect.Active | 12 ms (or on EI exit) | Initial wait before probing |
| Polling.Active minimum TS1s | 1024 TS1s (~64 µs at 2.5 GT/s) | Enough time for CDR lock |
| Polling.Active timeout | 24 ms | Allowed before exit-to-Detect if no TS2s |
| Polling.Configuration timeout | 48 ms | Before exit-to-Detect if TS2 handshake fails |
| Configuration.Complete timeout | 2 ms | Before exit to Recovery.Idle or Detect |
| Configuration.Idle timeout | 2 ms | Before exit to Recovery for equalization retry |
| Recovery.RcvrLock timeout | 24 ms | Before exit to RcvrCfg even without full handshake |
| Recovery.Equalization timeout | 24 ms | Per equalization phase |
| Recovery speed change electrical idle | 1–2 ms | Clock stabilisation at new rate |
| Max idle_to_rlock_transitioned | 256 (FFh) | Config.Idle→Recovery loop limit before fallback to Detect |