📈 What VCD Is and What SV Does with It

Value Change Dump (VCD) is a plain-text waveform file format defined in Verilog-2001. It records the signal values and times at which those values change. VCD files are read by waveform viewers (GTKWave, Verdi, QuestaSim, etc.) to display simulation waveforms.

SystemVerilog does not extend the VCD format itself — the format remains unchanged from Verilog-2001. Instead, SV defines how its additional types are mapped to Verilog types when they are dumped into a VCD file. Some SV types dump cleanly, others require structural decomposition, and a few cannot be dumped at all.

📋 SV-to-Verilog Type Mapping

When a signal of an SV type is included in a VCD dump, it is represented as the corresponding Verilog type shown in this table.

📋 Packed Arrays and Structures

All packed arrays and packed structures are collapsed into a single vector of reg for VCD dumping. Multiple packed dimensions are flattened — they appear as one continuous bit field in the waveform viewer.

// Declared as two packed dimensions
bit [3:0][7:0] packed_array;
// Dumped as: reg [31:0] packed_array (32-bit single vector)

// Packed struct
typedef struct packed {
  logic valid;
  logic[7:0] data;
} frame_t;
frame_t f;
// Dumped as: reg [8:0] f (9-bit single vector)

📋 Unpacked Structures

Unpacked structures appear in the VCD as named fork...join blocks, with each member element appearing inside the block as its mapped Verilog type. This makes them easy to distinguish in waveform viewers from variables declared inside ordinary begin...end blocks.

// SystemVerilog unpacked struct
typedef struct {
  int          addr;
  logic[7:0]  data;
  bit          valid;
} bus_pkt_t;
bus_pkt_t pkt;

// VCD representation — member order follows declaration order:
// fork pkt
//   integer addr;     (32 bits)
//   reg [7:0] data;   (8 bits)
//   reg valid;        (1 bit)
// join

📋 Enumerated Types

Enumerated type variables are dumped as their underlying integer type. By default this is a 32-bit integer, but if the enum has an explicit base type that base type governs the dump format.

// Default enum — dumps as 32-bit integer
typedef enum {IDLE, REQ, GRANT, DONE} state_t;
state_t state;
// VCD: integer state;  (IDLE=0, REQ=1, GRANT=2, DONE=3)

// Enum with explicit base type — dumps as that type
typedef enum byte {A, B, C} small_e;
small_e x;
// VCD: reg [7:0] x;  (8-bit reg, since base type is byte)

// The VCD value shows the ordinal integer — not the symbol name
// IDLE → 0, REQ → 1, etc.  Waveform tools may decode this back to
// symbol names if they recognise the enum declaration.

⛔ What Cannot Be Dumped

• Unpacked arrays — not dumped. This includes dynamic arrays, queues, and associative arrays. Fixed-size unpacked arrays of scalars also cannot be dumped.
• Automatic variables — not dumped. Automatic variables do not have a fixed storage location across the simulation run, so there is no stable address to track.

📋 Signed/Unsigned Information

The current VCD format does not provide a field to indicate whether a variable is signed or unsigned. All SV numeric types that map to reg or integer in VCD lose their signed/unsigned annotation — the waveform viewer has no way to distinguish them.

This is a known limitation of the VCD format rather than a SystemVerilog issue. Some proprietary waveform formats (e.g. FSDB) preserve this information through additional metadata outside the VCD specification.

📋 Quick Reference